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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:07 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:58:10 -0600 |
| commit | 3fd673cf363bc86ed42eff713d4e3506720e91a2 (patch) | |
| tree | 81c598c3b6e11409cf4f9b83d819e857ed95dbfe /doc | |
| parent | af35be6ac962a737005737ab479da93cac2f596f (diff) | |
| download | talos-obmc-uboot-3fd673cf363bc86ed42eff713d4e3506720e91a2.tar.gz talos-obmc-uboot-3fd673cf363bc86ed42eff713d4e3506720e91a2.zip | |
sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.sbc8548 | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index 6cbe12f1f5..5fa9c93685 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -100,6 +100,9 @@ Boot flash: Sodimm flash: intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + Note that this address reflects the default setting for + the JTAG debugging tools, but since the alignment is + rather inconvenient, u-boot puts it at 0xec00_0000. Jumpers: @@ -187,9 +190,12 @@ start end CS<n> width Desc. 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) f800_0000 f8b0_1fff CS5 - EPLD -fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) +[*] fb80 represents the default programmed by WR JTAG register files, + but u-boot places the flash at either ec00 or fc00 based on JP12. + The EPLD on CS5 demuxes the following devices at the following offsets: offset size width device |
