|author||Simon Glass <email@example.com>||2015-01-27 22:13:47 -0700|
|committer||Simon Glass <firstname.lastname@example.org>||2015-02-06 12:07:39 -0700|
x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <email@example.com> Reviewed-by: Bin Meng <firstname.lastname@example.org>
Diffstat (limited to 'doc')
1 files changed, 42 insertions, 5 deletions
diff --git a/doc/README.x86 b/doc/README.x86
index a9105f87c0..c699b795e2 100644
@@ -18,11 +18,11 @@ U-Boot supports running as a coreboot  payload on x86. So far only Link
on other x86 boards since coreboot deals with most of the low-level details.
U-Boot also supports booting directly from x86 reset vector without coreboot,
-aka raw support or bare support. Currently Link and Intel Crown Bay board
-support running U-Boot 'bare metal'.
+aka raw support or bare support. Currently Link, Intel Crown Bay and Intel
+Minnowboard Max support running U-Boot 'bare metal'.
-As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
-kernel as part of a FIT image. It also supports a compressed zImage.
+As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
+Linux kernel as part of a FIT image. It also supports a compressed zImage.
@@ -47,7 +47,7 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
to point to a new board. You can also change the Cache-As-RAM (CAR) related
settings here if the default values do not fit your new board.
-Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
little bit tricky, as generally it requires several binary blobs which are not
shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
not turned on by default in the U-Boot source tree. Firstly, you need turn it
@@ -110,6 +110,33 @@ Now you can build U-Boot and obtain u-boot.rom
$ make crownbay_defconfig
$ make all
+Intel Minnowboard Max instructions:
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the board directory:
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+You still need two more binary blobs. These come from the sample SPI image
+provided in the FSP (SPI.bin at the time of writing).
+Use ifdtool in the U-Boot tools directory to extract the images from that
+file, for example:
+ $ ./tools/ifdtool -x BayleyBay/SPI.bin
+ $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
+ $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+Now you can build U-Boot and obtain u-boot.rom
+$ make minnowmax_defconfig
+$ make all
Test with coreboot
For testing U-Boot as the coreboot payload, there are things that need be paid
@@ -130,6 +157,16 @@ symbol address of _start (in arch/x86/cpu/start.S).
If you want to use ELF as the coreboot payload, change U-Boot configuration to
use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
+To enable video you must enable these options in coreboot:
+ - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
+ - Keep VESA framebuffer
+At present it seems that for Minnowboard Max, coreboot does not pass through
+the video information correctly (it always says the resolution is 0x0). This
+works correctly for link though.
Modern CPUs usually require a special bit stream called microcode  to be