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| author | Andrew Bradford <andrew.bradford@kodakalaris.com> | 2015-06-03 12:37:39 -0400 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 03:03:18 -0600 |
| commit | afbbd413a3ef8a45155fcd083814ba645b09fcc7 (patch) | |
| tree | 33e1f29fa3bcb8865a9b21926c8e0df7ffc71310 /doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | |
| parent | 5c564226fc8948e435edea8eb8c5c4afbc5edef1 (diff) | |
| download | talos-obmc-uboot-afbbd413a3ef8a45155fcd083814ba645b09fcc7.tar.gz talos-obmc-uboot-afbbd413a3ef8a45155fcd083814ba645b09fcc7.zip | |
x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up. There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt')
0 files changed, 0 insertions, 0 deletions
