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author | Stefano Babic <sbabic@denx.de> | 2015-03-02 09:42:53 +0100 |
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committer | Stefano Babic <sbabic@denx.de> | 2015-03-02 09:42:53 +0100 |
commit | b9cb64825b5e6efeb715abd8b48d9b12f98973e9 (patch) | |
tree | d70d73a986308dee88474572006f5c60b10749be /doc/README.fsl-trustzone-components | |
parent | 4579dc37c3cce36d9521c26c6e82881393ec769e (diff) | |
parent | 1606b34aa50804227806971dbb6b82ea0bf81f55 (diff) | |
download | talos-obmc-uboot-b9cb64825b5e6efeb715abd8b48d9b12f98973e9.tar.gz talos-obmc-uboot-b9cb64825b5e6efeb715abd8b48d9b12f98973e9.zip |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'doc/README.fsl-trustzone-components')
-rw-r--r-- | doc/README.fsl-trustzone-components | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/doc/README.fsl-trustzone-components b/doc/README.fsl-trustzone-components new file mode 100644 index 0000000000..a3afd1f5f4 --- /dev/null +++ b/doc/README.fsl-trustzone-components @@ -0,0 +1,25 @@ +Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like +TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone +Address Space Controller). + +While most of the configuration related programming of these peripherals +is left to a root-of-trust security software layer (running in EL3 +privilege mode), but still some configurations of these peripherals +might be required while the bootloader is executing in EL3 privilege +mode. The following sections define how to turn on these features for +LS2085A like SoCs. + +TZPC-BP147 (TrustZone Protection Controller) +============================================ +- Depends on CONFIG_FSL_TZPC_BP147 configuration flag. +- Separates Secure World and Normal World on-chip RAM (OCRAM) spaces. +- Provides a programming model to set access control policy via the TZPC + TZDECPROT Registers. + +TZASC-400 (TrustZone Address Space Controller) +============================================== +- Depends on CONFIG_FSL_TZASC_400 configuration flag. +- Separates Secure World and Normal World external memory spaces for bus masters + such as processors and DMA-equipped peripherals. +- Supports 8 fully programmable address regions, initially inactive at reset, + and one base region, always active, that covers the remaining address space. |