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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-15 08:24:32 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-08-19 00:57:28 +0200 |
| commit | fcd69a1a57fb2af4d26201422095a4be9f36963e (patch) | |
| tree | dcd7a78e4dffdc7b0d1ad53da21345aa5887ca63 /cpu | |
| parent | a15b07104ca7bbb7093c9009c9ae1b58b4202d13 (diff) | |
| download | talos-obmc-uboot-fcd69a1a57fb2af4d26201422095a4be9f36963e.tar.gz talos-obmc-uboot-fcd69a1a57fb2af4d26201422095a4be9f36963e.zip | |
Clean up usage of icache_disable/dcache_disable
There is no point in disabling the icache on 7xx/74xx/86xx parts and not
also flushing the icache. All callers of invalidate_l1_instruction_cache()
call icache_disable() right after. Make it so icache_disable() calls
invalidate_l1_instruction_cache() for us.
Also, dcache_disable() already calls dcache_flush() so there is no point
in the explicit calls of dcache_flush().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/74xx_7xx/cache.S | 4 | ||||
| -rw-r--r-- | cpu/mpc86xx/cache.S | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index 3a745cbe03..eac4544ef2 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -245,6 +245,10 @@ _GLOBAL(icache_enable) * Disable L1 Instruction cache */ _GLOBAL(icache_disable) + mflr r4 + bl invalidate_l1_instruction_cache /* uses r3 */ + sync + mtlr r4 mfspr r3, HID0 li r5, 0 ori r5, r5, HID0_ICE diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index 2e4ea0239f..80ff68889b 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -232,6 +232,10 @@ _GLOBAL(icache_enable) * Disable L1 Instruction cache */ _GLOBAL(icache_disable) + mflr r4 + bl invalidate_l1_instruction_cache /* uses r3 */ + sync + mtlr r4 mfspr r3, HID0 li r5, 0 ori r5, r5, HID0_ICE |
