Revert merge of git://www.denx.de/git/u-boot-arm, commit 62479b18:

Reverting became necessary after it turned out that the patches in
the u-boot-arm repo were modified, and in some cases corrupted.

This reverts the following commits:

	066bebd6353e33af3adefc3404560871699e9961
	7a837b7310166ae8fc8b8d66d7ef01b60a80f9d6
	c88ae20580b2b01487b4cdcc8b2a113f551aee36
	a147e56f03871bba4f05058d5e04ce7deb010b04
	d6674e0e2a6a1f033945f78838566210d3f28c95
	8c8463cce44d849e37744749b32d38e1dfb12e50
	c98b47ad24b2d91f41c09a3d62d7f70ad84f4b7d
	8bf69d81782619187933a605f1a95ee1d069478d
	8c16cb0d3b971f46fbe77c072664c0f2dcd4471d
	a574a73852a527779234e73e17e7597fd8128882
	1377b5583a48021d983e1fd565f7d40c89e84d63
	1704dc20917b4f71e373e2c888497ee666d40380

Signed-off-by: Wolfgang Denk <wd@denx.de>

13 files changed, 188 insertions, 718 deletions

diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile
index 7701b03bbe..d5ac7d3fd9 100644
--- a/cpu/arm1136/Makefile
+++ b/cpu/arm1136/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o
+COBJS	= interrupts.o cpu.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 90e955303b..fa78eaa7f0 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -33,6 +33,9 @@
 
 #include <common.h>
 #include <command.h>
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+#include <asm/arch/omap2420.h>
+#endif
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
@@ -44,10 +47,10 @@ static unsigned long read_p15_c1 (void)
 	unsigned long value;
 
 	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
+						"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
+						: "=r" (value)
+						:
+						: "memory");
 	return value;
 }
 
diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/interrupts.c
index 8503b24a8e..491c902ace 100755..100644
--- a/cpu/arm1136/omap24xx/interrupts.c
+++ b/cpu/arm1136/interrupts.c
@@ -32,28 +32,31 @@
 
 #include <common.h>
 #include <asm/arch/bits.h>
-#include <asm/arch/omap2420.h>
+
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+# include <asm/arch/omap2420.h>
+#endif
 
 #define TIMER_LOAD_VAL 0
 
 /* macro to read the 32 bit timer */
-#define READ_TIMER (*((volatile ulong*)(CFG_TIMERBASE+TCRR)))
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
+
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+/* Use the IntegratorCP function from board/integratorcp.c */
+#else
 
 static ulong timestamp;
 static ulong lastinc;
 
-/*
- * nothing really to do with interrupts, just starts up a counter.
- */
-int interrupt_init(void)
+/* nothing really to do with interrupts, just starts up a counter. */
+int interrupt_init (void)
 {
 	int32_t val;
 
 	/* Start the counter ticking up */
-	/* reload value on overflow*/
-	*((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
-	/* mask to enable timer*/
-	val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0;
+	*((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
+	val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
 	*((int32_t *) (CFG_TIMERBASE + TCLR)) = val;	/* start timer */
 
 	reset_timer_masked(); /* init the timestamp and lastinc value */
@@ -63,99 +66,82 @@ int interrupt_init(void)
 /*
  * timer without interrupts
  */
-void reset_timer(void)
+void reset_timer (void)
 {
-	reset_timer_masked();
+	reset_timer_masked ();
 }
 
-ulong get_timer(ulong base)
+ulong get_timer (ulong base)
 {
-	return get_timer_masked() - base;
+	return get_timer_masked () - base;
 }
 
-void set_timer(ulong t)
+void set_timer (ulong t)
 {
 	timestamp = t;
 }
 
 /* delay x useconds AND perserve advance timstamp value */
-void udelay(unsigned long usec)
+void udelay (unsigned long usec)
 {
 	ulong tmo, tmp;
 
-	/* if "big" number, spread normalization to seconds */
-	if (usec >= 1000) {
-		/* start to normalize for usec to ticks per sec */
-		tmo = usec / 1000;
-		/* find number of "ticks" to wait to achieve target */
-		tmo *= CFG_HZ;
-		/* finish normalize. */
-		tmo /= 1000;
-	} else {
-		/* else small number, don't kill it prior to HZ multiply */
+	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
+		tmo *= CFG_HZ;			/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;			/* finish normalize. */
+	} else {					/* else small number, don't kill it prior to HZ multiply */
 		tmo = usec * CFG_HZ;
 		tmo /= (1000*1000);
 	}
-	/* get current timestamp */
-	tmp = get_timer(0);
-	if ((tmo + tmp + 1) < tmp)
-		/* setting this forward will roll time stamp */
-		/* reset "advancing" timestamp to 0, set lastinc value */
-		reset_timer_masked();
+
+	tmp = get_timer (0);		/* get current timestamp */
+	if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
 	else
-		/* else, set advancing stamp wake up time */
-		tmo	+= tmp;
-	while (get_timer_masked() < tmo)/* loop till event */
+		tmo	+= tmp;				/* else, set advancing stamp wake up time */
+	while (get_timer_masked () < tmo)/* loop till event */
 		/*NOP*/;
 }
 
-void reset_timer_masked(void)
+void reset_timer_masked (void)
 {
 	/* reset time */
-	/* capture current incrementer value time */
-	lastinc = READ_TIMER;
-	/* start "advancing" time stamp from 0 */
-	timestamp = 0;
+	lastinc = READ_TIMER;		/* capture current incrementer value time */
+	timestamp = 0;				/* start "advancing" time stamp from 0 */
 }
 
-ulong get_timer_masked(void)
+ulong get_timer_masked (void)
 {
-	ulong now = READ_TIMER;	/* current tick value */
+	ulong now = READ_TIMER;		/* current tick value */
 
-	/* normal mode (non roll) */
-	if (now >= lastinc)
-		/* move stamp forward with absolute diff ticks */
-		timestamp += (now - lastinc);
-	else
-		/* we have rollover of incrementer */
+	if (now >= lastinc)			/* normal mode (non roll) */
+		timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
+	else						/* we have rollover of incrementer */
 		timestamp += (0xFFFFFFFF - lastinc) + now;
 	lastinc = now;
 	return timestamp;
 }
 
 /* waits specified delay value and resets timestamp */
-void udelay_masked(unsigned long usec)
+void udelay_masked (unsigned long usec)
 {
 	ulong tmo;
 	ulong endtime;
 	signed long diff;
 
-	if (usec >= 1000) {
-		/* "big" number, spread normalization to seconds */
-		/* start to normalize for usec to ticks per sec */
-		tmo = usec / 1000;
-		/* find number of "ticks" to wait to achieve target */
-		tmo *= CFG_HZ;
-		tmo /= 1000;/* finish normalize. */
-	} else {
-		/* else small number, don't kill it prior to HZ multiply */
+	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
+		tmo *= CFG_HZ;			/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;			/* finish normalize. */
+	} else {					/* else small number, don't kill it prior to HZ multiply */
 		tmo = usec * CFG_HZ;
 		tmo /= (1000*1000);
 	}
-	endtime = get_timer_masked() + tmo;
+	endtime = get_timer_masked () + tmo;
 
 	do {
-		ulong now = get_timer_masked();
+		ulong now = get_timer_masked ();
 		diff = endtime - now;
 	} while (diff >= 0);
 }
@@ -172,9 +158,10 @@ unsigned long long get_ticks(void)
  * This function is derived from PowerPC code (timebase clock frequency).
  * On ARM it returns the number of timer ticks per second.
  */
-ulong get_tbclk(void)
+ulong get_tbclk (void)
 {
 	ulong tbclk;
 	tbclk = CFG_HZ;
 	return tbclk;
 }
+#endif /* !Integrator/CP */
diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile
deleted file mode 100644
index 1fc8eea451..0000000000
--- a/cpu/arm1136/mx31/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundatio; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= interrupts.o serial.o generic.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#######################################################################
-##
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
deleted file mode 100644
index 297d616d5e..0000000000
--- a/cpu/arm1136/mx31/generic.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx31-regs.h>
-
-static u32 mx31_decode_pll(u32 reg, u32 infreq)
-{
-	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
-	u32 pd =  (reg >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-	mfd += 1;
-	pd += 1;
-
-	return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-		(mfd * pd)) << 10;
-}
-
-u32 mx31_get_mpl_dpdgck_clk(void)
-{
-	u32 infreq;
-
-	if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-		infreq = CONFIG_MX31_CLK32 * 1024;
-	else
-		infreq = CONFIG_MX31_HCLK_FREQ;
-
-	return mx31_decode_pll(__REG(CCM_MPCTL), infreq); }
-
-u32 mx31_get_mcu_main_clk(void)
-{
-	/* For now we assume mpl_dpdgck_clk == mcu_main_clk
-	 * which should be correct for most boards
-	 */
-	return mx31_get_mpl_dpdgck_clk();
-}
-
-u32 mx31_get_ipg_clk(void)
-{
-	u32 freq = mx31_get_mcu_main_clk();
-	u32 pdr0 = __REG(CCM_PDR0);
-
-	freq /= ((pdr0 >> 3) & 0x7) + 1;
-	freq /= ((pdr0 >> 6) & 0x3) + 1;
-
-	return freq;
-}
-
-void mx31_dump_clocks(void)
-{
-	u32 cpufreq = mx31_get_mcu_main_clk();
-	printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
-	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
-}
-
-void mx31_gpio_mux(unsigned long mode)
-{
-	unsigned long reg, shift, tmp;
-
-	reg = IOMUXC_BASE + (mode & 0xfc);
-	shift = (~mode & 0x3) * 8;
-
-	tmp = __REG(reg);
-	tmp &= ~(0xff << shift);
-	tmp |= ((mode >> 8) & 0xff) << shift;
-	__REG(reg) = tmp;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	printf("CPU:   Freescale i.MX31 at %d MHz\n",
-		mx31_get_mcu_main_clk() / 1000000);
-	return 0;
-}
-#endif
diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c
deleted file mode 100644
index 189f6017ab..0000000000
--- a/cpu/arm1136/mx31/interrupts.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx31-regs.h>
-
-#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
-
-/* General purpose timers registers */
-#define GPTCR   __REG(TIMER_BASE) /* Control register */
-#define GPTPR  __REG(TIMER_BASE + 0x4) /* Prescaler register */
-#define GPTSR   __REG(TIMER_BASE + 0x8) /* Status register */
-#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15) /* Software reset */
-#define GPTCR_FRR       (1<<9)  /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6)  /* Clock source */
-#define GPTCR_TEN       (1)     /* Timer enable */
-
-/*
- * nothing really to do with interrupts, just starts up a counter.
- */
-int interrupt_init(void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	GPTCR = GPTCR_SWR;
-	for (i = 0; i < 100; i++) GPTCR = 0; /* We have no udelay by now */
-	GPTPR = 0; /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	GPTCR = 0;
-	/* Freerun Mode, PERCLK1 input*/
-	GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong val = GPTCNT;
-	return val;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay(unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if (usec >= 1000) {
-	/* "big" number, spread normalization to seconds */
-		/* start to normalize for usec to ticks per sec */
-		tmo = usec / 1000;
-		/* find number of "ticks" to wait to achieve target */
-		tmo *= CFG_HZ;
-		tmo /= 1000;	/* finish normalize. */
-	} else {
-		/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CFG_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer(0);		/* get current timestamp */
-	if ((tmo + tmp + 1) < tmp)
-		/* setting this forward will roll time stamp */
-		/* reset "advancing" timestamp to 0, set lastinc value */
-		reset_timer_masked();
-	else
-		/* else, set advancing stamp wake up time */
-		tmo	+= tmp;
-	while (get_timer_masked() < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_cpu(ulong addr)
-{
-	__REG16(WDOG_BASE) = 4;
-}
diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c
deleted file mode 100644
index f7e1b3b1a9..0000000000
--- a/cpu/arm1136/mx31/serial.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- */
-
-#include <common.h>
-
-#if defined CONFIG_MX31_UART
-
-#include <asm/arch/mx31.h>
-
-#define __REG(x)     (*((volatile u32 *)(x)))
-
-#ifdef CFG_MX31_UART1
-#define UART_PHYS 0x43f90000
-#elif defined(CFG_MX31_UART2)
-#define UART_PHYS 0x43f94000
-#elif defined(CFG_MX31_UART3)
-#define UART_PHYS 0x5000c000
-#elif defined(CFG_MX31_UART4)
-#define UART_PHYS 0x43fb0000
-#elif defined(CFG_MX31_UART5)
-#define UART_PHYS 0x43fb4000
-#else
-#error "define CFG_MX31_UARTx to use the mx31 UART driver"
-#endif
-
-/* Register definitions */
-#define URXD  0x0  /* Receiver Register */
-#define UTXD  0x40 /* Transmitter Register */
-#define UCR1  0x80 /* Control Register 1 */
-#define UCR2  0x84 /* Control Register 2 */
-#define UCR3  0x88 /* Control Register 3 */
-#define UCR4  0x8c /* Control Register 4 */
-#define UFCR  0x90 /* FIFO Control Register */
-#define USR1  0x94 /* Status Register 1 */
-#define USR2  0x98 /* Status Register 2 */
-#define UESC  0x9c /* Escape Character Register */
-#define UTIM  0xa0 /* Escape Timer Register */
-#define UBIR  0xa4 /* BRM Incremental Register */
-#define UBMR  0xa8 /* BRM Modulator Register */
-#define UBRC  0xac /* Baud Rate Count Register */
-#define UTS   0xb4 /* UART Test Register (mx31) */
-
-/* UART Control Register Bit Fields.*/
-#define  URXD_CHARRDY    (1<<15)
-#define  URXD_ERR        (1<<14)
-#define  URXD_OVRRUN     (1<<13)
-#define  URXD_FRMERR     (1<<12)
-#define  URXD_BRK        (1<<11)
-#define  URXD_PRERR      (1<<10)
-#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
-#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
-#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
-#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
-#define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
-#define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
-#define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
-#define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
-#define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
-#define  UCR1_SNDBRK     (1<<4)  /* Send break */
-#define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
-#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
-#define  UCR1_DOZE       (1<<1)  /* Doze */
-#define  UCR1_UARTEN     (1<<0)  /* UART enabled */
-#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
-#define  UCR2_CTS        (1<<12) /* Clear to send */
-#define  UCR2_ESCEN      (1<<11) /* Escape enable */
-#define  UCR2_PREN       (1<<8)  /* Parity enable */
-#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
-#define  UCR2_STPB       (1<<6)	 /* Stop */
-#define  UCR2_WS         (1<<5)	 /* Word size */
-#define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
-#define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
-#define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
-#define  UCR2_SRST 	 (1<<0)	 /* SW reset */
-#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
-#define  UCR3_PARERREN   (1<<12) /* Parity enable */
-#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
-#define  UCR3_DSR        (1<<10) /* Data set ready */
-#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
-#define  UCR3_RI         (1<<8)  /* Ring indicator */
-#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
-#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
-#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
-#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
-#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC  	 (1<<5)  /* IR special case */
-#define  UCR4_TCEN  	 (1<<3)  /* Transmit complete interrupt enable */
-#define  UCR4_BKEN  	 (1<<2)  /* Break condition interrupt enable */
-#define  UCR4_OREN  	 (1<<1)  /* Receiver overrun interrupt enable */
-#define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
-#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
-#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
-#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
-#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD  	 (1<<12) /* RTS delta */
-#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
-#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
-#define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
-#define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
-#define  USR1_RXDS  	 (1<<6)	 /* Receiver idle interrupt flag */
-#define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
-#define  USR1_AWAKE 	 (1<<4)	 /* Aysnc wake interrupt flag */
-#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE  	 (1<<12) /* Idle condition */
-#define  USR2_IRINT 	 (1<<8)	 /* Serial infrared interrupt flag */
-#define  USR2_WAKE  	 (1<<7)	 /* Wake */
-#define  USR2_RTSF  	 (1<<4)	 /* RTS edge interrupt flag */
-#define  USR2_TXDC  	 (1<<3)	 /* Transmitter complete */
-#define  USR2_BRCD  	 (1<<2)	 /* Break condition */
-#define  USR2_ORE        (1<<1)	 /* Overrun error */
-#define  USR2_RDR        (1<<0)	 /* Recv data ready */
-#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
-#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
-#define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
-#define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
-#define  UTS_TXFULL 	 (1<<4)	 /* TxFIFO full */
-#define  UTS_RXFULL 	 (1<<3)	 /* RxFIFO full */
-#define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
-	u32 clk = mx31_get_ipg_clk();
-
-	if (!gd->baudrate)
-		gd->baudrate = CONFIG_BAUDRATE;
-
-	__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
-	__REG(UART_PHYS + UBIR) = 0xf;
-	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-
-}
-
-int serial_getc(void)
-{
-	while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
-	return __REG(UART_PHYS + URXD);
-}
-
-void serial_putc(const char c)
-{
-	__REG(UART_PHYS + UTXD) = c;
-
-	/* wait for transmitter to be ready */
-	while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer  */
-int serial_tstc(void)
-{
-	/* If receive fifo is empty, return false */
-	if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
-		return 0;
-	return 1;
-}
-
-void serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc(*s++);
-	}
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init(void)
-{
-	__REG(UART_PHYS + UCR1) = 0x0;
-	__REG(UART_PHYS + UCR2) = 0x0;
-
-	while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
-
-	__REG(UART_PHYS + UCR3) = 0x0704;
-	__REG(UART_PHYS + UCR4) = 0x8000;
-	__REG(UART_PHYS + UESC) = 0x002b;
-	__REG(UART_PHYS + UTIM) = 0x0;
-
-	__REG(UART_PHYS + UTS) = 0x0;
-
-	serial_setbrg();
-
-	__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | \
-					UCR2_TXEN | UCR2_SRST;
-
-	__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
-	return 0;
-}
-
-
-#endif /* CONFIG_MX31 */
diff --git a/cpu/arm1136/omap24xx/Makefile b/cpu/arm1136/omap24xx/Makefile
deleted file mode 100644
index 39b0a82811..0000000000
--- a/cpu/arm1136/omap24xx/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundatio; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= interrupts.o
-SOBJS	= start.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm1136/omap24xx/start.S b/cpu/arm1136/omap24xx/start.S
deleted file mode 100644
index 5634312970..0000000000
--- a/cpu/arm1136/omap24xx/start.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- *
- *  Copyright (c) 2001	Marius Gr??ger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Z??pke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/omap2420.h>
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl	/* get addr for global reset reg */
-	mov	r3, #0x2	/* full reset pll+mpu */
-	str	r3, [r1]	/* force reset */
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PM_RSTCTRL_WKUP
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index 56009d0fb3..8b765f1e80 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -30,6 +30,9 @@
 
 #include <config.h>
 #include <version.h>
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+#include <asm/arch/omap2420.h>
+#endif
 .globl _start
 _start: b	reset
 #ifdef CONFIG_ONENAND_IPL
@@ -435,4 +438,22 @@ fiq:
 arm1136_cache_flush:
 		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
 		mov	pc, lr			@ back to caller
+
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+/* Use the IntegratorCP function from board/integratorcp/platform.S */
+#else
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl	/* get addr for global reset reg */
+	mov	r3, #0x2	/* full reset pll+mpu */
+	str	r3, [r1]	/* force reset */
+	mov	r0, r0
+_loop_forever:
+	b	_loop_forever
+rstctl:
+	.word	PM_RSTCTRL_WKUP
+
+#endif
 #endif	/* CONFIG_ONENAND_IPL */
diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S
index 79bc692c14..a87c112eca 100644
--- a/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -3,11 +3,6 @@
  *
  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  *
- * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
- * Changed:
- * Made board specific defines such as DDR timing and PLL
- * dividers. These should be set in the board config file
- *
  * Partially based on TI sources, original copyrights follow:
  */
 
@@ -161,17 +156,17 @@ WaitPPL2Loop:
 
 	/* Program the PLL Multiplier */
 	ldr	r6, PLL2_PLLM
-	mov	r2, $CFG_DAVINCI_PLL2_PLLM
+	mov	r2, $0x17	/* 162 MHz */
 	str	r2, [r6]
 
 	/* Program the PLL2 Divisor Value */
 	ldr	r6, PLL2_DIV2
-	mov	r3, $CFG_DAVINCI_PLL2_DIV2
+	mov	r3, $0x01
 	str	r3, [r6]
 
 	/* Program the PLL2 Divisor Value */
 	ldr	r6, PLL2_DIV1
-	mov	r4, $CFG_DAVINCI_PLL2_DIV1
+	mov	r4, $0x0b	/* 54 MHz */
 	str	r4, [r6]
 
 	/* PLL2 DIV2 MMR */
@@ -278,7 +273,7 @@ checkDDRStatClkStop:
 	bne	checkDDRStatClkStop
 
 	/*------------------------------------------------------*
-	 * Program DDR2 MMRs					*
+	 * Program DDR2 MMRs for 162MHz Setting			*
 	 *------------------------------------------------------*/
 
 	/* Program PHY Control Register */
@@ -293,12 +288,12 @@ checkDDRStatClkStop:
 
 	/* Program SDRAM TIM-0 Config Register */
 	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL
+	ldr	r7, SDTIM0_VAL_162MHz
 	str	r7, [r6]
 
 	/* Program SDRAM TIM-1 Config Register */
 	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL
+	ldr	r7, SDTIM1_VAL_162MHz
 	str	r7, [r6]
 
 	/* Program the SDRAM Bank Config Control Register */
@@ -440,7 +435,7 @@ WaitLoop:
 
 	/* Program the PLL Multiplier */
 	ldr	r6, PLL1_PLLM
-	mov	r3, $CFG_DAVINCI_PLL1_PLLM
+	mov	r3, $0x15	/* For 594MHz */
 	str	r3, [r6]
 
 	/* Wait for PLL to Reset Properly */
@@ -472,7 +467,7 @@ PLL1Lock:
 	nop
 
 	/*------------------------------------------------------*
-	 * AEMIF configuration for NAND/NOR Flash		*
+	 * AEMIF configuration for NOR Flash (double check)     *
 	 *------------------------------------------------------*/
 	ldr	r0, _PINMUX0
 	ldr	r1, _DEV_SETTING
@@ -484,12 +479,6 @@ PLL1Lock:
 	orr	r2, r2, r1
 	str	r2, [r0]
 
-	ldr	r0, ACFG2
-	ldr	r1, ACFG2_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
 	ldr	r0, ACFG3
 	ldr	r1, ACFG3_VAL
 	ldr	r2, [r0]
@@ -508,12 +497,6 @@ PLL1Lock:
 	and	r1, r2, r1
 	str	r1, [r0]
 
-	ldr	r0, NANDFCR
-	ldr	r1, NANDFCR_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
 	/*--------------------------------------*
 	 * VTP manual Calibration               *
 	 *--------------------------------------*/
@@ -577,36 +560,24 @@ _PINMUX1:
 	.word	0x01c40004		/* Device Configuration Registers */
 
 _DEV_SETTING:
-	.word	CFG_DAVINCI_PINMUX_0
+	.word	0x00000c1f
 
 WAITCFG:
 	.word	0x01e00004
 WAITCFG_VAL:
-	.word	CFG_DAVINCI_WAITCFG
-ACFG2:
-	.word	0x01e00010
-ACFG2_VAL:
-	.word	CFG_DAVINCI_ACFG2
+	.word	0
 ACFG3:
 	.word	0x01e00014
 ACFG3_VAL:
-	.word	CFG_DAVINCI_ACFG3
+	.word	0x3ffffffd
 ACFG4:
 	.word	0x01e00018
 ACFG4_VAL:
-	.word	CFG_DAVINCI_ACFG4
+	.word	0x3ffffffd
 ACFG5:
 	.word	0x01e0001c
 ACFG5_VAL:
-	.word	CFG_DAVINCI_ACFG5
-NANDFCR:
-	.word	0x01e00060
-NANDFCR_VAL:
-#ifdef CFG_DAVINCI_NANDCE
-	.word	(1 << (CFG_DAVINCI_NANDCE - 2))
-#else
-	.word	0x00000000
-#endif
+	.word	0x3ffffffd
 
 MDCTL_DDR2:
 	.word	0x01c41a34
@@ -628,27 +599,33 @@ PSC_FLAG_CLEAR:
 PSC_GEM_FLAG_CLEAR:
 	.word	0xfffffeff
 
-/* DDR2 MMR & CONFIGURATION VALUES */
+/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
 DDRCTL:
 	.word	0x200000e4
 DDRCTL_VAL:
-	.word	CFG_DAVINCI_DDRCTL
+	.word	0x50006405
 SDREF:
 	.word	0x2000000c
 SDREF_VAL:
-	.word	CFG_DAVINCI_SDREF
+	.word	0x000005c3
 SDCFG:
 	.word	0x20000008
 SDCFG_VAL:
-	.word	CFG_DAVINCI_SDCFG
+#ifdef	DDR_4BANKS
+	.word	0x00178622
+#elif defined DDR_8BANKS
+	.word	0x00178632
+#else
+#error "Unknown DDR configuration!!!"
+#endif
 SDTIM0:
 	.word	0x20000010
-SDTIM0_VAL:
-	.word	CFG_DAVINCI_SDTIM0
+SDTIM0_VAL_162MHz:
+	.word	0x28923211
 SDTIM1:
 	.word	0x20000014
-SDTIM1_VAL:
-	.word	CFG_DAVINCI_SDTIM1
+SDTIM1_VAL_162MHz:
+	.word	0x0016c722
 VTPIOCR:
 	.word	0x200000f0	/* VTP IO Control register */
 DDRVTPR:
@@ -722,7 +699,7 @@ PLL2_DIV_MASK:
 MMARG_BRF0:
 	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
 MMARG_BRF0_VAL:
-	.word	CFG_DAVINCI_MMARG_BRF0
+	.word	0x00444400
 
 DDR2_START_ADDR:
 	.word	0x80000000
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 3257f83a2f..127be9fcd4 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 	dummy = emif_addr->NANDF3ECC;
 	dummy = emif_addr->NANDF4ECC;
 
-	emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
+	emif_addr->NANDFCR |= (1 << 8);
 }
 
 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
@@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
 
 	n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
 
-	region = (CFG_DAVINCI_NANDCE - 1);
+	region = 1;
 	while (n--) {
 		tmp = nand_davinci_readecc(mtd, region);
 		*ecc_code++ = tmp;
@@ -311,9 +311,40 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i
 
 static void nand_flash_init(void)
 {
-	/* All EMIF initialization is done in lowlevel_init.S
-	 * and config values are in the board config files
-	 */
+	u_int32_t	acfg1 = 0x3ffffffc;
+	u_int32_t	acfg2 = 0x3ffffffc;
+	u_int32_t	acfg3 = 0x3ffffffc;
+	u_int32_t	acfg4 = 0x3ffffffc;
+	emifregs	emif_regs;
+
+	/*------------------------------------------------------------------*
+	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
+	 *                                                                  *
+	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
+	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
+	 *                                                                  *
+	 *------------------------------------------------------------------*/
+	 acfg1 = 0
+	 	| (0 << 31 )	/* selectStrobe */
+	 	| (0 << 30 )	/* extWait */
+	 	| (1 << 26 )	/* writeSetup	10 ns */
+	 	| (3 << 20 )	/* writeStrobe	40 ns */
+	 	| (1 << 17 )	/* writeHold	10 ns */
+	 	| (1 << 13 )	/* readSetup	10 ns */
+	 	| (5 << 7 )	/* readStrobe	60 ns */
+	 	| (1 << 4 )	/* readHold	10 ns */
+	 	| (3 << 2 )	/* turnAround	?? ns */
+	 	| (0 << 0 )	/* asyncSize	8-bit bus */
+	 	;
+
+	emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
+
+	emif_regs->AWCCR |= 0x10000000;
+	emif_regs->AB1CR = acfg1;	/* 0x08244128 */;
+	emif_regs->AB2CR = acfg2;
+	emif_regs->AB3CR = acfg3;
+	emif_regs->AB4CR = acfg4;
+	emif_regs->NANDFCR = 0x00000101;
 }
 
 int board_nand_init(struct nand_chip *nand)
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 4797797b6d..8bb8b45713 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -42,9 +42,9 @@
 
 typedef volatile struct {
 	u_int32_t	pid12;
-	u_int32_t	emumgt;
-	u_int32_t	na1;
-	u_int32_t	na2;
+	u_int32_t	emumgt_clksped;
+	u_int32_t	gpint_en;
+	u_int32_t	gpdir_dat;
 	u_int32_t	tim12;
 	u_int32_t	tim34;
 	u_int32_t	prd12;
@@ -52,12 +52,21 @@ typedef volatile struct {
 	u_int32_t	tcr;
 	u_int32_t	tgcr;
 	u_int32_t	wdtcr;
+	u_int32_t	tlgc;
+	u_int32_t	tlmr;
 } davinci_timer;
 
 davinci_timer		*timer = (davinci_timer *)CFG_TIMERBASE;
 
 #define TIMER_LOAD_VAL	(CFG_HZ_CLOCK / CFG_HZ)
-#define TIM_CLK_DIV	16
+#define READ_TIMER	timer->tim34
+
+/*
+ * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
+ * around of timestamp already after min ~159s, divide it, e.g. by 16.
+ * timestamp will then wrap around all min ~42min
+ */
+#define DIV(x)		((x) >> 4)
 
 static ulong timestamp;
 static ulong lastinc;
@@ -67,50 +76,63 @@ int timer_init(void)
 	/* We are using timer34 in unchained 32-bit mode, full speed */
 	timer->tcr = 0x0;
 	timer->tgcr = 0x0;
-	timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
+	timer->tgcr = 0x06;
 	timer->tim34 = 0x0;
 	timer->prd34 = TIMER_LOAD_VAL;
 	lastinc = 0;
+	timer->tcr = 0x80 << 16;
 	timestamp = 0;
-	timer->tcr = 2 << 22;
 
 	return(0);
 }
 
 void reset_timer(void)
 {
-	timer->tcr = 0x0;
-	timer->tim34 = 0;
-	lastinc = 0;
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return(get_timer_masked() - base);
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+void reset_timer_masked(void)
+{
+	lastinc = DIV(READ_TIMER);
 	timestamp = 0;
-	timer->tcr = 2 << 22;
 }
 
-static ulong get_timer_raw(void)
+ulong get_timer_raw(void)
 {
-	ulong now = timer->tim34;
+	ulong now = DIV(READ_TIMER);
 
 	if (now >= lastinc) {
 		/* normal mode */
 		timestamp += now - lastinc;
 	} else {
 		/* overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
+		timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
 	}
 	lastinc = now;
 	return timestamp;
 }
 
-ulong get_timer(ulong base)
-{
-	return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); }
-
-void set_timer(ulong t)
+ulong get_timer_masked(void)
 {
-	timestamp = t;
+	return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
 }
 
-void udelay(unsigned long usec)
+void udelay_masked(unsigned long usec)
 {
 	ulong tmo;
 	ulong endtime;
@@ -118,7 +140,7 @@ void udelay(unsigned long usec)
 
 	tmo = CFG_HZ_CLOCK / 1000;
 	tmo *= usec;
-	tmo /= (1000 * TIM_CLK_DIV);
+	tmo /= 1000;
 
 	endtime = get_timer_raw() + tmo;
 
@@ -143,5 +165,8 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk(void)
 {
-	return CFG_HZ;
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return(tbclk);
 }