Merge branch 'kumar'

5 files changed, 202 insertions, 106 deletions

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index d179d701bd..2205dca024 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -30,7 +30,7 @@ LIB	= $(obj)lib$(CPU).a
 
 START	= start.o resetvec.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
+COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
 	  pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
 	  $(COBJS-y)
 
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index fdb9ecbd50..c0ff1d5120 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -31,6 +31,8 @@
 #include <asm/processor.h>
 #include <ioports.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -122,6 +124,34 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 }
 #endif
 
+/* We run cpu_init_early_f in AS = 1 */
+void cpu_init_early_f(void)
+{
+	set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		1, 0, BOOKE_PAGESZ_4K, 0);
+
+	/* set up CCSR if we want it moved */
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	{
+		u32 temp;
+
+		set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			1, 1, BOOKE_PAGESZ_4K, 0);
+
+		temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
+		out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12);
+
+		temp = in_be32((volatile u32 *)CFG_CCSRBAR);
+	}
+#endif
+
+	init_laws();
+	invalidate_tlb(0);
+	init_tlbs();
+}
+
 /*
  * Breathe some life into the CPU...
  *
@@ -134,13 +164,15 @@ void cpu_init_f (void)
 	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 	extern void m8560_cpm_reset (void);
 
+	disable_tlb(14);
+	disable_tlb(15);
+
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
-
 #ifdef CONFIG_CPM2
 	config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 #endif
@@ -222,11 +254,15 @@ void cpu_init_f (void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_CLEAR_LAW0
+#ifdef CONFIG_FSL_LAW
+	disable_law(0);
+#else
 	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	/* clear alternate boot location LAW (used for sdram, or ddr bank) */
 	ecm->lawar0 = 0;
 #endif
+#endif
 
 #if defined(CONFIG_L2_CACHE)
 	volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index adc9c4dd40..abc63c414b 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -27,6 +27,7 @@
 #include <i2c.h>
 #include <spd.h>
 #include <asm/mmu.h>
+#include <asm/fsl_law.h>
 
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@ -1022,7 +1023,6 @@ spd_sdram(void)
 static unsigned int
 setup_laws_and_tlbs(unsigned int memsize)
 {
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 	unsigned int tlb_size;
 	unsigned int law_size;
 	unsigned int ram_tlb_index;
@@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize)
 	ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
 	while (ram_tlb_address < (memsize * 1024 * 1024)
 	      && ram_tlb_index < 16) {
-		mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
-		mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
-		mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
-		mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
-			(MAS3_SX|MAS3_SW|MAS3_SR)));
-		asm volatile("isync;msync;tlbwe;isync");
-
-		debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
-		debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
-		debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
-		debug("DDR: MAS3=0x%08x\n",
-			FSL_BOOKE_MAS3(ram_tlb_address, 0,
-			              (MAS3_SX|MAS3_SW|MAS3_SR)));
+		set_tlb(1, ram_tlb_address, ram_tlb_address,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, ram_tlb_index, tlb_size, 1);
 
 		ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
 		ram_tlb_index++;
@@ -1098,12 +1088,10 @@ setup_laws_and_tlbs(unsigned int memsize)
 	/*
 	 * Set up LAWBAR for all of DDR.
 	 */
-	ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-	ecm->lawar1 = (LAWAR_EN
-		       | LAWAR_TRGT_IF_DDR
-		       | (LAWAR_SIZE & law_size));
-	debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
-	debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
+
+#ifdef CONFIG_FSL_LAW
+	set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
+#endif
 
 	/*
 	 * Confirm that the requested amount of memory was mapped.
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index b489d2ff0c..e8e5eb297d 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -143,84 +143,8 @@ _start_e500:
 	li	r1,0x0f00
 	mtspr	IVOR15,r1	/* 15: Debug */
 
-
-	/*
-	 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
-	 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
-	 * region before we can access any CCSR registers such as L2
-	 * registers, Local Access Registers,etc. We will also re-allocate
-	 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
-	 *
-	 * Please refer to board-specif directory for TLB1 entry configuration.
-	 * (e.g. board/<yourboard>/init.S)
-	 *
-	 */
-	bl	tlb1_entry
-	mr	r5,r0
-	lwzu	r4,0(r5)	/* how many TLB1 entries we actually use */
-	mtctr	r4
-
-0:	lwzu	r6,4(r5)
-	lwzu	r7,4(r5)
-	lwzu	r8,4(r5)
-	lwzu	r9,4(r5)
-	mtspr	MAS0,r6
-	mtspr	MAS1,r7
-	mtspr	MAS2,r8
-	mtspr	MAS3,r9
-	isync
-	msync
-	tlbwe
-	isync
-	bdnz	0b
-
-1:
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/* Special sequence needed to update CCSRBAR itself */
-	lis	r4,CFG_CCSRBAR_DEFAULT@h
-	ori	r4,r4,CFG_CCSRBAR_DEFAULT@l
-
-	lis	r5,CFG_CCSRBAR@h
-	ori	r5,r5,CFG_CCSRBAR@l
-	srwi	r6,r5,12
-	stw	r6,0(r4)
-	isync
-
-	lis	r5,0xffff
-	ori	r5,r5,0xf000
-	lwz	r5,0(r5)
-	isync
-
-	lis	r3,CFG_CCSRBAR@h
-	lwz	r5,CFG_CCSRBAR@l(r3)
-	isync
-#endif
-
-
-	/* set up local access windows, defined at board/<boardname>/init.S */
-	lis	r7,CFG_CCSRBAR@h
-	ori	r7,r7,CFG_CCSRBAR@l
-
-	bl	law_entry
-	mr	r6,r0
-	lwzu	r5,0(r6)	/* how many windows we actually use */
-	mtctr	r5
-
-	li	r2,0x0c28	/* the first pair is reserved for */
-	li	r1,0x0c30	/* boot-over-rio-or-pci */
-
-0:	lwzu	r4,4(r6)
-	lwzu	r3,4(r6)
-	stwx	r4,r7,r2
-	stwx	r3,r7,r1
-	addi	r2,r2,0x0020
-	addi	r1,r1,0x0020
-	bdnz	0b
-
 	/* Clear and set up some registers. */
-	li      r0,0
-	mtmsr   r0
-	li	r0,0x0000
+	li      r0,0x0000
 	lis	r1,0xffff
 	mtspr	DEC,r0			/* prevent dec exceptions */
 	mttbl	r0			/* prevent fit & wdt exceptions */
@@ -230,18 +154,13 @@ _start_e500:
 	mtspr	ESR,r0			/* clear exception syndrome register */
 	mtspr	MCSR,r0			/* machine check syndrome register */
 	mtxer	r0			/* clear integer exception register */
-	lis	r1,0x0002		/* set CE bit (Critical Exceptions) */
-	ori	r1,r1,0x1200		/* set ME/DE bit */
-	mtmsr	r1			/* change MSR */
-	isync
 
 	/* Enable Time Base and Select Time Base Clock */
 	lis	r0,HID0_EMCP@h		/* Enable machine check */
 #if defined(CONFIG_ENABLE_36BIT_PHYS)
-	ori	r0,r0,(HID0_TBEN|HID0_ENMAS7)@l	/* Enable Timebase & MAS7 */
-#else
-	ori	r0,r0,HID0_TBEN@l	/* enable Timebase */
+	ori	r0,r0,HID0_ENMAS7@l	/* Enable MAS7 */
 #endif
+	ori	r0,r0,HID0_TBEN@l	/* Enable Timebase */
 	mtspr	HID0,r0
 
 	li	r0,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
@@ -262,6 +181,58 @@ _start_e500:
 	mtspr	DBCR0,r0
 #endif
 
+	/* create a temp mapping in AS=1 to the boot window */
+	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
+	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
+
+	lis     r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+	lis     r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+	mtspr   MAS0,r6
+	mtspr   MAS1,r7
+	mtspr   MAS2,r8
+	mtspr   MAS3,r9
+	isync
+	msync
+	tlbwe
+
+	/* create a temp mapping in AS=1 to the stack */
+	lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
+	ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
+
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
+
+	lis     r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l
+
+	lis     r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+	mtspr   MAS0,r6
+	mtspr   MAS1,r7
+	mtspr   MAS2,r8
+	mtspr   MAS3,r9
+	isync
+	msync
+	tlbwe
+
+	lis	r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
+	ori	r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
+	lis	r7,switch_as@h
+	ori	r7,r7,switch_as@l
+
+	mtspr	SPRN_SRR0,r7
+	mtspr	SPRN_SRR1,r6
+	rfi
+
+switch_as:
 /* L1 DCache is used for initial RAM */
 
 	/* Allocate Initial RAM in data cache.
@@ -321,6 +292,14 @@ _start_cont:
 	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
 
 	GET_GOT
+	bl	cpu_init_early_f
+
+	/* switch back to AS = 0 */
+	lis	r3,(MSR_CE|MSR_ME|MSR_DE)@h
+	ori	r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
+	mtmsr	r3
+	isync
+
 	bl	cpu_init_f
 	bl	board_init_f
 	isync
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
new file mode 100644
index 0000000000..b2c799ad12
--- /dev/null
+++ b/cpu/mpc85xx/tlb.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+void set_tlb(u8 tlb, u32 epn, u64 rpn,
+	     u8 perms, u8 wimge,
+	     u8 ts, u8 esel, u8 tsize, u8 iprot)
+{
+	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+
+	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
+	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
+	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
+	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
+	_mas7 = rpn >> 32;
+
+	mtspr(MAS0, _mas0);
+	mtspr(MAS1, _mas1);
+	mtspr(MAS2, _mas2);
+	mtspr(MAS3, _mas3);
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+	mtspr(MAS7, _mas7);
+#endif
+	asm volatile("isync;msync;tlbwe;isync");
+}
+
+void disable_tlb(u8 esel)
+{
+	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+
+	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
+	_mas1 = 0;
+	_mas2 = 0;
+	_mas3 = 0;
+	_mas7 = 0;
+
+	mtspr(MAS0, _mas0);
+	mtspr(MAS1, _mas1);
+	mtspr(MAS2, _mas2);
+	mtspr(MAS3, _mas3);
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+	mtspr(MAS7, _mas7);
+#endif
+	asm volatile("isync;msync;tlbwe;isync");
+}
+
+void invalidate_tlb(u8 tlb)
+{
+	if (tlb == 0)
+		mtspr(MMUCSR0, 0x4);
+	if (tlb == 1)
+		mtspr(MMUCSR0, 0x2);
+}
+
+void init_tlbs(void)
+{
+	int i;
+
+	for (i = 0; i < num_tlb_entries; i++) {
+		set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
+			tlb_table[i].perms, tlb_table[i].wimge,
+			tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
+			tlb_table[i].iprot);
+	}
+
+	return ;
+}
+