diff options
| author | wdenk <wdenk> | 2003-09-02 22:48:03 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-09-02 22:48:03 +0000 |
| commit | 12f34241cb9679c27a1ab3561766562f5a515eff (patch) | |
| tree | e6408a1701c7dabf3e2ceb1326ce2f5cc8657c96 /cpu/ppc4xx | |
| parent | 326428cc8bbdddb30920a96b672abd0d59833ce4 (diff) | |
| download | talos-obmc-uboot-12f34241cb9679c27a1ab3561766562f5a515eff.tar.gz talos-obmc-uboot-12f34241cb9679c27a1ab3561766562f5a515eff.zip | |
* Add support for PPChameleon Eval Board
* Add support for P3G4 board
* Fix problem with MGT5100 FEC driver: add "early" MAC address
initialization
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 10 | ||||
| -rw-r--r-- | cpu/ppc4xx/miiphy.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 3 |
3 files changed, 9 insertions, 6 deletions
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 1d7c0c9a78..ab9b2e5eaf 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -50,15 +50,15 @@ int checkcpu (void) { #if defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ - defined(CONFIG_IOP480) || \ - defined(CONFIG_440) || \ - defined(CONFIG_405EP) + defined(CONFIG_405EP) || \ + defined(CONFIG_440) || \ + defined(CONFIG_IOP480) uint pvr = get_pvr(); #endif #if defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ - defined(CONFIG_IOP480) || \ - defined(CONFIG_405EP) + defined(CONFIG_405EP) || \ + defined(CONFIG_IOP480) DECLARE_GLOBAL_DATA_PTR; ulong clock = gd->cpu_clk; diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 0606ebef9d..e719a330f6 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -101,6 +101,7 @@ int miiphy_read (unsigned char addr, unsigned char reg, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; + sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; sta_reg = sta_reg | (addr << 5); /* Phy address */ out32 (EMAC_STACR, sta_reg); @@ -156,6 +157,7 @@ int miiphy_write (unsigned char addr, unsigned char reg, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; + sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ memcpy (&sta_reg, &value, 2); /* put in data */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index e3e92afa84..215a925b93 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -702,7 +702,8 @@ _start: /* NEVER RETURNS! */ bl board_init_f /* run first part of init code (from Flash) */ -#endif /* CONFIG_405GP || CONFIG_405CR */ +#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ + /*----------------------------------------------------------------------- */ /*****************************************************************************/ |
