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| author | Stefan Roese <sr@denx.de> | 2008-06-26 17:36:39 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-07-11 13:18:14 +0200 |
| commit | 5de851403b01489b493fa83137ad990b8ce60d1c (patch) | |
| tree | 5cec8babce21b513667055b34157efec7182b3e6 /cpu/ppc4xx/cpu_init.c | |
| parent | d1631fe1a05b063ccaf62ea892a8887b829847d1 (diff) | |
| download | talos-obmc-uboot-5de851403b01489b493fa83137ad990b8ce60d1c.tar.gz talos-obmc-uboot-5de851403b01489b493fa83137ad990b8ce60d1c.zip | |
ppc4xx: Rework 440GX UIC handling
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.
Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/cpu_init.c')
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index ac64279051..e2d0402781 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -138,9 +138,10 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) u32 val; #endif + reconfigure_pll(CFG_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) @@ -273,6 +274,18 @@ cpu_init_f (void) reset_4xx_watchdog(); #endif /* CONFIG_WATCHDOG */ +#if defined(CONFIG_440GX) + /* Take the GX out of compatibility mode + * Travis Sawyer, 9 Mar 2004 + * NOTE: 440gx user manual inconsistency here + * Compatibility mode and Ethernet Clock select are not + * correct in the manual + */ + mfsdr(sdr_mfr, val); + val &= ~0x10000000; + mtsdr(sdr_mfr,val); +#endif /* CONFIG_440GX */ + #if defined(CONFIG_460EX) /* * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and |
