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| author | Stefan Roese <sr@denx.de> | 2007-03-01 21:16:02 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-01 21:16:02 +0100 |
| commit | c8556d0e0b27c57c0860f55736761a18c7a115f2 (patch) | |
| tree | 4ab1cc720d191688c72fc4ebcfb49c384c0a0228 /cpu/ppc4xx/44x_spd_ddr2.c | |
| parent | ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35 (diff) | |
| parent | 8c12045a3b06c5b6675d3fe02fbc9f545988129a (diff) | |
| download | talos-obmc-uboot-c8556d0e0b27c57c0860f55736761a18c7a115f2.tar.gz talos-obmc-uboot-c8556d0e0b27c57c0860f55736761a18c7a115f2.zip | |
Merge with /home/stefan/git/u-boot/denx-merge-sr
Diffstat (limited to 'cpu/ppc4xx/44x_spd_ddr2.c')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index fe0f2b6ea4..35b23152f3 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -48,10 +48,10 @@ * Defines *-----------------------------------------------------------------------------*/ #ifndef TRUE -#define TRUE 1 +#define TRUE 1 #endif #ifndef FALSE -#define FALSE 0 +#define FALSE 0 #endif #define SDRAM_DDR1 1 @@ -199,9 +199,9 @@ static void program_DQS_calibration(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); #ifdef HARD_CODED_DQS /* calibration test with hardvalues */ -static void test(void); +static void test(void); #else -static void DQS_calibration_process(void); +static void DQS_calibration_process(void); #endif #if defined(DEBUG) static void ppc440sp_sdram_register_dump(void); @@ -354,12 +354,12 @@ static unsigned long sdram_memsize(void) * .data sections. It also cannot call routines that require these sections. *-----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- - * Function: initdram + * Function: initdram * Description: Configures SDRAM memory banks for DDR operation. - * Auto Memory Configuration option reads the DDR SDRAM EEPROMs - * via the IIC bus and then configures the DDR SDRAM memory - * banks appropriately. If Auto Memory Configuration is - * not used, it is assumed that no DIMM is plugged + * Auto Memory Configuration option reads the DDR SDRAM EEPROMs + * via the IIC bus and then configures the DDR SDRAM memory + * banks appropriately. If Auto Memory Configuration is + * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ long int initdram(int board_type) { @@ -589,10 +589,10 @@ static void get_spd_info(unsigned long *dimm_populated, #ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { - if (is_ecc_enabled()) - puts(" (ECC enabled)"); - else - puts(" (ECC not enabled)"); + if (is_ecc_enabled()) + puts(" (ECC enabled)"); + else + puts(" (ECC not enabled)"); } #endif @@ -1165,7 +1165,7 @@ static void program_initplr(unsigned long *dimm_populated, /****************************************************** ** Assumption: if more than one DIMM, all DIMMs are the same - ** as already checked in check_memory_type + ** as already checked in check_memory_type ******************************************************/ if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) { |
