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| author | Wheatley Travis <Travis.Wheatley@freescale.com> | 2008-05-02 13:35:15 -0700 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-05-09 20:46:48 +0200 |
| commit | f5a24259190c388c2527bdc49fee34577d862cc7 (patch) | |
| tree | e77d0df2fc72dfd1a26c993785dae2250738eb2d /cpu/mpc86xx | |
| parent | 4d31cdc45d3592a5545a649fb5a24b458a4e4b72 (diff) | |
| download | talos-obmc-uboot-f5a24259190c388c2527bdc49fee34577d862cc7.tar.gz talos-obmc-uboot-f5a24259190c388c2527bdc49fee34577d862cc7.zip | |
7450 and 86xx L2 cache invalidate bug corrections
The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.
This patch addresses both of these bugs.
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Acked-By: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'cpu/mpc86xx')
| -rw-r--r-- | cpu/mpc86xx/cache.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index f316b3ec13..2e4ea0239f 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate) invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2I@h + andis. r3, r3, L2CR_L2I@h bne invl2 blr |
