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| author | Jon Loeliger <jdl@freescale.com> | 2006-08-29 09:48:49 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-08-29 09:48:49 -0500 |
| commit | cd6d73d5b895a5935ac4fde0a356288142a584e0 (patch) | |
| tree | cf88428292b75ccb1080c7a045dca698520ca807 /cpu/mpc86xx | |
| parent | 778d45049ce5927b65b3ff1d8e6692b654bdd49e (diff) | |
| download | talos-obmc-uboot-cd6d73d5b895a5935ac4fde0a356288142a584e0.tar.gz talos-obmc-uboot-cd6d73d5b895a5935ac4fde0a356288142a584e0.zip | |
Remove bogus msync and use volatile asm.
Diffstat (limited to 'cpu/mpc86xx')
| -rw-r--r-- | cpu/mpc86xx/spd_sdram.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index a4b9d54c7b..44b0d4133c 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -834,7 +834,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); #endif - asm("sync;isync"); + asm volatile("sync;isync"); udelay(500); /* @@ -1032,7 +1032,7 @@ unsigned int enable_ddr(unsigned int ddr_num) */ if (config == 0x02) { ddr->err_disable = 0x00000000; - asm("sync;isync;"); + asm volatile("sync;isync;"); ddr->err_sbe = 0x00ff0000; ddr->err_int_en = 0x0000000d; sdram_cfg_1 |= 0x20000000; /* ECC_EN */ @@ -1325,7 +1325,7 @@ ddr_enable_ecc(unsigned int dram_size) */ debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); ddr1->err_disable = 0x00000000; - asm("sync;isync;msync"); + asm volatile("sync;isync"); debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); } |
