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authorJon Loeliger <jdl@freescale.com>2008-06-06 10:48:31 -0500
committerJon Loeliger <jdl@freescale.com>2008-06-06 10:48:31 -0500
commit1a247ba7fa5fb09f56892a09a990f03ce564b3e2 (patch)
tree9dab0ef013cc6dc7883454808ecf6ba4d7a7a94e /cpu/mpc86xx
parent2c289e320dcfb3760e99cf1d765cb067194a1202 (diff)
parent8155efbd7ae9c65564ca98affe94631d612ae088 (diff)
downloadtalos-obmc-uboot-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.gz
talos-obmc-uboot-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.zip
Merge commit 'wd/master'
Diffstat (limited to 'cpu/mpc86xx')
-rw-r--r--cpu/mpc86xx/cpu.c4
-rw-r--r--cpu/mpc86xx/spd_sdram.c2
-rw-r--r--cpu/mpc86xx/start.S14
3 files changed, 11 insertions, 9 deletions
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 3c7476445d..e26bf3671d 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -26,6 +26,7 @@
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
+#include <asm/mmu.h>
#include <mpc86xx.h>
#include <asm/fsl_law.h>
@@ -268,13 +269,14 @@ dma_xfer(void *dest, uint count, void *src)
/*
* Print out the state of various machine registers.
- * Currently prints out LAWs and BR0/OR0
+ * Currently prints out LAWs, BR0/OR0, and BATs
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CFG_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
+ print_bats();
print_laws();
printf ("Local Bus Controller Registers\n"
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 8485841a45..5cc0c266f0 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -528,7 +528,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
caslat -= 1;
else if (busfreq > max_data_rate) {
printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
- busfreq, max_data_rate);
+ busfreq, max_data_rate);
return 0;
}
}
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index c71c92659d..c39dc4681d 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -486,25 +486,25 @@ setup_bats:
.globl early_bats
early_bats:
/* IBAT 5 */
- lis r4, CFG_IBAT5L@h
+ lis r4, CFG_IBAT5L@h
ori r4, r4, CFG_IBAT5L@l
- lis r3, CFG_IBAT5U@h
+ lis r3, CFG_IBAT5U@h
ori r3, r3, CFG_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
isync
/* DBAT 5 */
- lis r4, CFG_DBAT5L@h
+ lis r4, CFG_DBAT5L@h
ori r4, r4, CFG_DBAT5L@l
- lis r3, CFG_DBAT5U@h
+ lis r3, CFG_DBAT5U@h
ori r3, r3, CFG_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
isync
/* IBAT 6 */
- lis r4, CFG_IBAT6L@h
+ lis r4, CFG_IBAT6L@h
ori r4, r4, CFG_IBAT6L@l
lis r3, CFG_IBAT6U@h
ori r3, r3, CFG_IBAT6U@l
@@ -513,9 +513,9 @@ early_bats:
isync
/* DBAT 6 */
- lis r4, CFG_DBAT6L@h
+ lis r4, CFG_DBAT6L@h
ori r4, r4, CFG_DBAT6L@l
- lis r3, CFG_DBAT6U@h
+ lis r3, CFG_DBAT6U@h
ori r3, r3, CFG_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
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