ColdFire: Add M5208EVB and MCF520x CPU support

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

6 files changed, 199 insertions, 14 deletions

diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index 829273617b..52751be3e4 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -26,6 +26,7 @@
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 
 cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
 is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
 is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
 is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
@@ -36,6 +37,9 @@ is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
 
 ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 
+ifneq (,$(findstring CONFIG_M5208,$(is5208)))
+PLATFORM_CPPFLAGS += -mcpu=5208
+endif
 ifneq (,$(findstring CONFIG_M5249,$(is5249)))
 PLATFORM_CPPFLAGS += -mcpu=5249
 endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 32d6c40da0..2cfe6311d0 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -34,6 +34,72 @@
 #include <asm/immap.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef	CONFIG_M5208
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+	udelay(1000);
+
+	rcm->rcr = RCM_RCR_SOFTRST;
+
+	/* we don't return! */
+	return 0;
+};
+
+int checkcpu(void)
+{
+	char buf1[32], buf2[32];
+
+	printf("CPU:   Freescale Coldfire MCF5208\n"
+	       "       CPU CLK %s MHz BUS CLK %s MHz\n",
+	       strmhz(buf1, gd->cpu_clk),
+	       strmhz(buf2, gd->bus_clk));
+	return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdt->sr = 0x5555;
+	wdt->sr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
+r */
+	wdt->sr = 0xAAAA;
+	wdt->cr = 0;	/* disable watchdog timer */
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->cr = 0;	/* disable watchdog */
+
+	/* set timeout and enable watchdog */
+	wdt->mr =
+		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
+	wdt->sr = 0x5555; /* reset watchdog counter */
+	wdt->sr = 0xAAAA;
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+#endif				/* #ifdef CONFIG_M5208 */
+
 #ifdef  CONFIG_M5271
 /*
  * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 11f70b0dbf..7cea6558fd 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -101,6 +101,95 @@ void init_fbcs(void)
 }
 #endif
 
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+	/* Disable the watchdog if we aren't using it */
+	wdg->cr = 0;
+#endif
+
+	scm1->mpr = 0x77777777;
+	scm1->pacra = 0;
+	scm1->pacrb = 0;
+	scm1->pacrc = 0;
+	scm1->pacrd = 0;
+	scm1->pacre = 0;
+	scm1->pacrf = 0;
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+	icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (CONFIG_SYS_UART_PORT) {
+	case 0:
+		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		break;
+	case 1:
+		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		gpio->par_timer &=
+		    (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+		gpio->par_timer |=
+		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		gpio->par_feci2c &=
+		    (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		gpio->par_feci2c &=
+		    (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_fec |=
+		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+		gpio->par_feci2c |=
+		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+	} else {
+		gpio->par_fec &=
+		    (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
+		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* CONFIG_M5208 */
+
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 0181e4b416..dff8c6aa88 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,13 +59,19 @@ void dtimer_intr_setup(void)
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
 	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
+#if defined(CONFIG_M5208)
+	intp->imrl0 = 0xFFFFFFFF;
+	intp->imrh0 = 0xFFFFFFFF;
+#else
 	intp->imrl0 |= 0x1;
+#endif
 
 	enable_interrupts();
 	return 0;
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index c93a5180eb..b485e1cccc 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -30,11 +30,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks (void)
 {
+#if defined(CONFIG_M5208)
+	volatile pll_t *pll = (pll_t *) MMAP_PLL;
+
+	pll->odr = CONFIG_SYS_PLL_ODR;
+	pll->fdr = CONFIG_SYS_PLL_FDR;
+#endif
+
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
@@ -77,7 +82,7 @@ int get_clocks (void)
 #endif
 
 	gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index ba6b8843e4..0dd4de5160 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -120,6 +120,12 @@ _start:
 	nop
 	move.w #0x2700,%sr
 
+#if defined(CONFIG_M5208)
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set MBAR address + valid flag */
 	move.c	%d0, %MBAR
@@ -195,15 +201,6 @@ _after_flashbar_copy:
 	movec	%d0, %RAMBAR1
 #endif
 
-#if 0
-	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0, %d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-#endif
-
 	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
@@ -340,6 +337,24 @@ _int_handler:
 
 /*------------------------------------------------------------------------------*/
 /* cache functions */
+#ifdef	CONFIG_M5208
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+
+	move.l	#0x80000200, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	nop
+
+	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+#endif
+
 #ifdef	CONFIG_M5271
 	.globl	icache_enable
 icache_enable: