diff options
| author | Alexey Brodkin <Alexey.Brodkin@synopsys.com> | 2015-12-14 17:14:46 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2016-02-20 11:19:53 +0300 |
| commit | 379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1 (patch) | |
| tree | dee63afdf0dd287b0daef4b3552513babff0fea3 /configs | |
| parent | 86a0df732853d1a11eb3eaa3cda688d9ef7b34e5 (diff) | |
| download | talos-obmc-uboot-379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1.tar.gz talos-obmc-uboot-379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1.zip | |
arc: cache - accommodate different L1 cache line lengths
ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.
Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.
With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/axs101_defconfig | 1 | ||||
| -rw-r--r-- | configs/tb100_defconfig | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index a541d9d17f..b79dd3ce5d 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,6 +1,5 @@ CONFIG_ARC=y CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=750000000 CONFIG_SYS_TEXT_BASE=0x81000000 diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 27ea43ff97..053b74ca3d 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -1,5 +1,4 @@ CONFIG_ARC=y -CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_TARGET_TB100=y CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=500000000 |
