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authorYork Sun <yorksun@freescale.com>2015-11-04 10:03:23 -0800
committerYork Sun <yorksun@freescale.com>2015-12-13 18:27:28 -0800
commit3901978d42b7008b13e7e9b67bea12a51cc5847b (patch)
treedf251b3cd312040e5108e8acdd9fa5cc2750acec /configs/P1010RDB-PA_36BIT_NAND_defconfig
parentc4243ac9e2713897a63dcdc3a96bf088fdb49866 (diff)
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armv8/ls2080ardb: Update DDR settings for four chip-select case
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
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