Merge git://git.denx.de/u-boot-mpc85xx

38 files changed, 1700 insertions, 97 deletions

diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig
new file mode 100644
index 0000000000..feca03aeef
--- /dev/null
+++ b/board/Arcturus/ucp1020/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_UCP1020
+
+config SYS_BOARD
+	string
+	default "ucp1020"
+
+config SYS_VENDOR
+	string
+	default "Arcturus"
+
+config SYS_CONFIG_NAME
+	string
+	default "UCP1020"
+
+config SPI_FLASH
+	bool
+	default y
+
+config SPI_PCI
+	bool
+	default y
+
+choice
+	prompt "Target image select"
+
+config TARGET_UCP1020_NOR
+	bool "NOR flash u-boot image"
+
+config TARGET_UCP1020_SPIFLASH
+	bool "SPI flash u-boot image"
+
+endchoice
+
+if TARGET_UCP1020_SPIFLASH
+config UCBOOT
+	bool
+	default y
+
+config SPIFLASH
+	bool
+	default y
+endif
+
+endif
diff --git a/board/Arcturus/ucp1020/MAINTAINERS b/board/Arcturus/ucp1020/MAINTAINERS
new file mode 100644
index 0000000000..e4a4718188
--- /dev/null
+++ b/board/Arcturus/ucp1020/MAINTAINERS
@@ -0,0 +1,7 @@
+UCP1020 BOARD
+M:	Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
+S:	Maintained
+F:	board/Arcturus/ucp1020/
+F:	include/configs/UCP1020.h
+F:	configs/UCP1020_defconfig
+F:	configs/UCP1020_SPIFLASH_defconfig
diff --git a/board/Arcturus/ucp1020/Makefile b/board/Arcturus/ucp1020/Makefile
new file mode 100644
index 0000000000..35c88b98a9
--- /dev/null
+++ b/board/Arcturus/ucp1020/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013-2015 Arcturus Networks, Inc.
+# based on board/freescale/p1_p2_rdb_pc/Makefile
+# original copyright follows:
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y        += ucp1020.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o
+obj-y        += cmd_arc.o
+
+endif
diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README
new file mode 100644
index 0000000000..555c4ef79f
--- /dev/null
+++ b/board/Arcturus/ucp1020/README
@@ -0,0 +1,54 @@
+The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
+product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
+DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
+
+Information on the generic product family can be found here:
+	http://www.arcturusnetworks.com/products/ucp1020
+
+The UCP1020 several configurable options
+========================================
+
+- the selection of populated phy(s):
+	KSZ9031 (current default for eTSEC 1 and 3)
+
+- the selection of boot location:
+	SPI Flash or NOR flash
+
+The UCP1020 includes 2 default configurations
+=============================================
+NOR boot image:
+	configs/UCP1020_defconfig
+SPI boot image:
+	configs/UCP1020_SPIFLASH_defconfig
+
+The UCP1020 adds an additional command in cmd_arc.c to access and program
+SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
+HW Addresses.
+
+
+Build example
+=============
+
+make distclean
+make UCP1020_defconfig
+make
+
+Default Scripts
+===============
+A default upgrade scripts is included in the default environment variable example:
+
+B$ run tftpflash
+
+Dual Environment
+================
+
+This build enables dual / failover environment environment.
+
+NOR Flash Partition declarations and scripts
+============================================
+Several scripts are available to allow TFTP of images and programming directly
+into defined NOR flash partitions. Examples:
+
+B$ run program0
+B$ run program1
+B$ run program2
diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c
new file mode 100644
index 0000000000..fa6b4853f9
--- /dev/null
+++ b/board/Arcturus/ucp1020/cmd_arc.c
@@ -0,0 +1,231 @@
+/*
+ * Command for accessing Arcturus factory environment.
+ *
+ * Copyright 2013-2015 Arcturus Networks Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ *
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include <asm/io.h>
+
+#ifndef CONFIG_SF_DEFAULT_SPEED
+#   define CONFIG_SF_DEFAULT_SPEED	1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+#   define CONFIG_SF_DEFAULT_MODE	SPI_MODE0
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+#   define CONFIG_SF_DEFAULT_CS		0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+#   define CONFIG_SF_DEFAULT_BUS	0
+#endif
+
+#define MAX_SERIAL_SIZE 15
+#define MAX_HWADDR_SIZE 17
+
+#define FIRM_ADDR1 (0x200 - sizeof(smac))
+#define FIRM_ADDR2 (0x400 - sizeof(smac))
+#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
+#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
+
+static struct spi_flash *flash;
+char smac[4][18];
+
+static int ishwaddr(char *hwaddr)
+{
+	if (strlen(hwaddr) == MAX_HWADDR_SIZE)
+		if (hwaddr[2] == ':' &&
+		    hwaddr[5] == ':' &&
+		    hwaddr[8] == ':' &&
+		    hwaddr[11] == ':' &&
+		    hwaddr[14] == ':')
+			return 0;
+	return -1;
+}
+
+static int set_arc_product(int argc, char *const argv[])
+{
+	int err = 0;
+	char *mystrerr = "ERROR: Failed to save factory info in spi location";
+
+	if (argc != 5)
+		return -1;
+
+	/* Check serial number */
+	if (strlen(argv[1]) != MAX_SERIAL_SIZE)
+		return -1;
+
+	/* Check HWaddrs */
+	if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
+		return -1;
+
+	strcpy(smac[3], argv[1]);
+	strcpy(smac[2], argv[2]);
+	strcpy(smac[1], argv[3]);
+	strcpy(smac[0], argv[4]);
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+
+	/*
+	 * Save factory defaults
+	 */
+
+	if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) {
+		printf("%s: %s [1]\n", __func__, mystrerr);
+		err++;
+	}
+	if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) {
+		printf("%s: %s [2]\n", __func__, mystrerr);
+		err++;
+	}
+
+	if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) {
+		printf("%s: %s [3]\n", __func__, mystrerr);
+		err++;
+	}
+
+	if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) {
+		printf("%s: %s [4]\n", __func__, mystrerr);
+		err++;
+	}
+
+	if (err == 4) {
+		printf("%s: %s [ALL]\n", __func__, mystrerr);
+		return -2;
+	}
+
+	return 0;
+}
+
+int get_arc_info(void)
+{
+	int location = 1;
+	char *myerr = "ERROR: Failed to read all 4 factory info spi locations";
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+
+	if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) {
+		location++;
+		if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) {
+			location++;
+			if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac),
+					   smac)) {
+				location++;
+				if (spi_flash_read(flash, FIRM_ADDR4,
+						   sizeof(smac), smac)) {
+					printf("%s: %s\n", __func__, myerr);
+					return -2;
+				}
+			}
+		}
+	}
+	if (smac[3][0] != 0) {
+		if (location > 1)
+			printf("Using region %d\n", location);
+		printf("SERIAL: ");
+		if (smac[3][0] == 0xFF) {
+			printf("\t<not found>\n");
+		} else {
+			printf("\t%s\n", smac[3]);
+			setenv("SERIAL", smac[3]);
+		}
+	}
+
+	if (strcmp(smac[2], "00:00:00:00:00:00") == 0)
+		return 0;
+
+	printf("HWADDR0:");
+	if (smac[2][0] == 0xFF) {
+		printf("\t<not found>\n");
+	} else {
+		char *ret = getenv("ethaddr");
+
+		if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
+			setenv("ethaddr", smac[2]);
+			printf("\t%s (factory)\n", smac[2]);
+		} else {
+			printf("\t%s\n", ret);
+		}
+	}
+
+	if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
+		setenv("eth1addr", smac[2]);
+		setenv("eth2addr", smac[2]);
+		return 0;
+	}
+
+	printf("HWADDR1:");
+	if (smac[1][0] == 0xFF) {
+		printf("\t<not found>\n");
+	} else {
+		char *ret = getenv("eth1addr");
+
+		if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
+			setenv("eth1addr", smac[1]);
+			printf("\t%s (factory)\n", smac[1]);
+		} else {
+			printf("\t%s\n", ret);
+		}
+	}
+
+	if (strcmp(smac[0], "00:00:00:00:00:00") == 0) {
+		setenv("eth2addr", smac[1]);
+		return 0;
+	}
+
+	printf("HWADDR2:");
+	if (smac[0][0] == 0xFF) {
+		printf("\t<not found>\n");
+	} else {
+		char *ret = getenv("eth2addr");
+
+		if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
+			setenv("eth2addr", smac[0]);
+			printf("\t%s (factory)\n", smac[0]);
+		} else {
+			printf("\t%s\n", ret);
+		}
+	}
+
+	return 0;
+}
+
+static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	const char *cmd;
+	int ret = -1;
+
+	cmd = argv[1];
+	--argc;
+	++argv;
+
+	if (strcmp(cmd, "product") == 0) {
+		ret = set_arc_product(argc, argv);
+		goto done;
+	}
+	if (strcmp(cmd, "info") == 0) {
+		ret = get_arc_info();
+		goto done;
+	}
+done:
+	if (ret == -1)
+		return CMD_RET_USAGE;
+
+	return ret;
+}
+
+U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
+	   "Arcturus product command sub-system",
+	   "product serial hwaddr0 hwaddr1 hwaddr2    - save Arcturus factory env\n"
+	   "info                                      - show Arcturus factory env\n\n");
diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c
new file mode 100644
index 0000000000..42fbae058d
--- /dev/null
+++ b/board/Arcturus/ucp1020/ddr.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 536870912u,
+	.capacity = 536870912u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1650,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 14050,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 75000,
+	.trp_ps = 13500,
+	.tras_ps = 40000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 75000,
+	.trtp_ps = 75000,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 30000,
+};
+
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+	       strmhz(buf, sysinfo.freq_ddrbus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+			 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	if (pdimm->primary_sdram_width == 64)
+		popts->data_bus_width = 0;
+	else if (pdimm->primary_sdram_width == 32)
+		popts->data_bus_width = 1;
+	else
+		printf("Error in DDR bus width configuration!\n");
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c
new file mode 100644
index 0000000000..7d40905b56
--- /dev/null
+++ b/board/Arcturus/ucp1020/law.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_VSC7385_ENET
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
new file mode 100644
index 0000000000..236b0d0de5
--- /dev/null
+++ b/board/Arcturus/ucp1020/spl.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
+	env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/Arcturus/ucp1020/spl_minimal.c b/board/Arcturus/ucp1020/spl_minimal.c
new file mode 100644
index 0000000000..5bdefb8a0d
--- /dev/null
+++ b/board/Arcturus/ucp1020/spl_minimal.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
+ * original copyright follows:
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c
new file mode 100644
index 0000000000..fd7134f5cf
--- /dev/null
+++ b/board/Arcturus/ucp1020/tlb.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/tlb.c
+ * original copyright follows:
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI memory 1.5G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O effective: 192K  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+#endif /* not SPL */
+
+#ifdef CONFIG_SYS_NAND_BASE
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+	/* *I*G - eSDHC/eSPI/NAND boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_1G, 1),
+
+#endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
new file mode 100644
index 0000000000..0fc2bac55d
--- /dev/null
+++ b/board/Arcturus/ucp1020/ucp1020.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <spi_flash.h>
+#include <mmc.h>
+#include <linux/ctype.h>
+#include <asm/fsl_serdes.h>
+#include <asm/gpio.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include "ucp1020.h"
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+	/* TO DO: It's actially have to be in spi/ */
+}
+
+/*
+ * To be compatible with cmd_gpio
+ */
+int name_to_gpio(const char *name)
+{
+	int gpio = 31 - simple_strtoul(name, NULL, 10);
+
+	if (gpio < 16)
+		gpio = -1;
+
+	return gpio;
+}
+
+void board_gpio_init(void)
+{
+	int i;
+	char envname[8], *val;
+
+	for (i = 0; i < GPIO_MAX_NUM; i++) {
+		sprintf(envname, "GPIO%d", i);
+		val = getenv(envname);
+		if (val) {
+			char direction = toupper(val[0]);
+			char level = toupper(val[1]);
+
+			if (direction == 'I') {
+				gpio_direction_input(i);
+			} else {
+				if (direction == 'O') {
+					if (level == '1')
+						gpio_direction_output(i, 1);
+					else
+						gpio_direction_output(i, 0);
+				}
+			}
+		}
+	}
+
+	val = getenv("PCIE_OFF");
+	if (val) {
+		gpio_direction_input(GPIO_PCIE1_EN);
+		gpio_direction_input(GPIO_PCIE2_EN);
+	} else {
+		gpio_direction_output(GPIO_PCIE1_EN, 1);
+		gpio_direction_output(GPIO_PCIE2_EN, 1);
+	}
+
+	val = getenv("SDHC_CDWP_OFF");
+	if (!val) {
+		ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+		setbits_be32(&gur->pmuxcr,
+			     (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+	}
+}
+
+int board_early_init_f(void)
+{
+	return 0;	/* Just in case. Could be disable in config file */
+}
+
+int checkboard(void)
+{
+	printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
+	board_gpio_init();
+	printf("SD/MMC: 4-bit Mode\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+		MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#if defined(CONFIG_PHY_MICREL_KSZ9021)
+	int regval;
+	static int cnt;
+
+	if (cnt++ == 0)
+		printf("PHYs address [");
+
+	if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
+		regval =
+		    ksz9021_phy_extended_read(phydev,
+					      MII_KSZ9021_EXT_STRAP_STATUS);
+		/*
+		 * min rx data delay
+		 */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+					   0x6666);
+		/*
+		 * max rx/tx clock delay, min rx/tx control
+		 */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+					   0xf6f6);
+		printf("0x%x", (regval & 0x1f));
+	} else {
+		printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
+	}
+	if (cnt == 3)
+		printf("] ");
+	else
+		printf(",");
+#endif
+
+#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
+	regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
+	if (regval >= 0)
+		printf(" (ADDR 0x%x) ", regval & 0x1f);
+#endif
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	static char newkernelargs[256];
+	static u8 id1[16];
+	static u8 id2;
+	struct mmc *mmc;
+	char *sval, *kval;
+
+	if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
+		printf("Error reading i2c IDT6V49205B information!\n");
+	} else {
+		printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
+		i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+		if (!(id1[1] & 0x02)) {
+			id1[1] |= 0x02;
+			i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+			asm("nop; nop");
+		}
+	}
+
+	if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
+		printf("Error reading i2c NCT72 information!\n");
+	else
+		printf("NCT72(0x%x): ready\n", id2);
+
+	kval = getenv("kernelargs");
+
+	mmc = find_mmc_device(0);
+	if (mmc)
+		if (!mmc_init(mmc)) {
+			printf("MMC/SD card detected\n");
+			if (kval) {
+				int n = strlen(defkargs);
+				char *tmp = strstr(kval, defkargs);
+
+				*tmp = 0;
+				strcpy(newkernelargs, kval);
+				strcat(newkernelargs, " ");
+				strcat(newkernelargs, mmckargs);
+				strcat(newkernelargs, " ");
+				strcat(newkernelargs, &tmp[n]);
+				setenv("kernelargs", newkernelargs);
+			} else {
+				setenv("kernelargs", mmckargs);
+			}
+		}
+	get_arc_info();
+
+	if (kval) {
+		sval = getenv("SERIAL");
+		if (sval) {
+			strcpy(newkernelargs, "SN=");
+			strcat(newkernelargs, sval);
+			strcat(newkernelargs, " ");
+			strcat(newkernelargs, kval);
+			setenv("kernelargs", newkernelargs);
+		}
+	} else {
+		printf("Error reading kernelargs env variable!\n");
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+#ifdef CONFIG_TSEC2
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
+			puts("eTSEC2 is in sgmii mode.\n");
+			tsec_info[num].flags |= TSEC_SGMII;
+			tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+		}
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+	const char *soc_usb_compat = "fsl-usb2-dr";
+	int err, usb1_off, usb2_off;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	/* Delete eLBC node as it is muxed with USB2 controller */
+	if (hwconfig("usb2")) {
+		const char *soc_elbc_compat = "fsl,p1020-elbc";
+		int off = fdt_node_offset_by_compatible(blob, -1,
+							soc_elbc_compat);
+		if (off < 0) {
+			printf
+			    ("WARNING: could not find compatible node %s: %s\n",
+			     soc_elbc_compat, fdt_strerror(off));
+			return off;
+		}
+		err = fdt_del_node(blob, off);
+		if (err < 0) {
+			printf("WARNING: could not remove %s: %s\n",
+			       soc_elbc_compat, fdt_strerror(err));
+		}
+		return err;
+	}
+#endif
+
+/* Delete USB2 node as it is muxed with eLBC */
+	usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
+	if (usb1_off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(usb1_off));
+		return usb1_off;
+	}
+	usb2_off =
+	    fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
+	if (usb2_off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(usb2_off));
+		return usb2_off;
+	}
+	err = fdt_del_node(blob, usb2_off);
+	if (err < 0) {
+		printf("WARNING: could not remove %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(err));
+	}
+	return 0;
+}
+#endif
diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h
new file mode 100644
index 0000000000..243459c446
--- /dev/null
+++ b/board/Arcturus/ucp1020/ucp1020.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __UCP1020_H__
+#define __UCP1020_H__
+
+#define GPIO0		31
+#define GPIO1		30
+#define GPIO2		29
+#define GPIO3		28
+#define GPIO4		27
+#define GPIO5		26
+#define GPIO6		25
+#define GPIO7		24
+#define GPIO8		23
+#define GPIO9		22
+#define GPIO10		21
+#define GPIO11		20
+#define GPIO12		19
+#define GPIO13		18
+#define GPIO14		17
+#define GPIO15		16
+#define GPIO_MAX_NUM	16
+
+#define GPIO_SDHC_CD	GPIO8
+#define GPIO_SDHC_WP	GPIO9
+#define GPIO_USB_PCTL0	GPIO10
+#define GPIO_PCIE1_EN	GPIO11
+#define GPIO_PCIE2_EN	GPIO10
+#define GPIO_USB_PCTL1	GPIO11
+
+#define GPIO_WD		GPIO15
+
+static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
+static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
+
+int get_arc_info(void);
+
+#endif
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index 9e4132c64e..e9cbd515a1 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -43,16 +43,16 @@ void fsl_dp_disable_console(void)
  */
 static void dp_ddr_restore(void)
 {
-	volatile u64 *src, *dst;
+	u64 *src, *dst;
 	int i;
 	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
 
 	/* get the address of ddr date from SPARECR3 */
-	src = (u64 *)in_be32(&scfg->sparecr[2]);
-	dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+	src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
+	dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
 
 	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
-		*dst++ = *src++;
+		*dst-- = *src--;
 
 	flush_dcache();
 }
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 52d20219ec..51ce9c328d 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -115,4 +115,18 @@ void qixis_write_i2c(unsigned int reg, u8 value);
 			qixis_write_i2c(offsetof(struct qixis, reg), value)
 #endif
 
+/* Use for SDHC adapter card type identification and operation */
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#define QIXIS_SDID_MASK                         0x07
+#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45         0x1	/* eMMC Card Rev4.5 */
+#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY   0x2	/* SD/MMC Legacy Card */
+#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44         0x3	/* eMMC Card Rev4.4 */
+#define QIXIS_ESDHC_ADAPTER_TYPE_RSV            0x4	/* Reserved */
+#define QIXIS_ESDHC_ADAPTER_TYPE_MMC            0x5	/* MMC Card */
+#define QIXIS_ESDHC_ADAPTER_TYPE_SD             0x6	/* SD Card Rev2.0 3.0 */
+#define QIXIS_ESDHC_NO_ADAPTER                  0x7	/* No Card is Present*/
+#define QIXIS_SDCLKIN		0x08
+#define QIXIS_SDCLKOUT		0x02
+#endif
+
 #endif
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
index 7723f580db..441d6a3e61 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -172,8 +172,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
 		if (port == FM1_DTSEC3) {
 			fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
-			fdt_setprop(fdt, offset, "phy-connection-type",
-				    "rgmii", 5);
+			fdt_setprop_string(fdt, offset, "phy-connection-type",
+					   "rgmii");
 			fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
 		}
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
@@ -207,7 +207,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			break;
 		}
 		fdt_delprop(fdt, offset, "phy-connection-type");
-		fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "qsgmii");
 		fdt_status_okay_by_alias(fdt, "emi1_slot2");
 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 		/* XFI interface */
@@ -219,7 +220,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 		/* no PHY for XFI */
 		fdt_delprop(fdt, offset, "phy-handle");
 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
-		fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
+		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
 	}
 }
 
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
index dc554d4d3a..297e63a6ee 100644
--- a/board/freescale/t102xrdb/MAINTAINERS
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -8,3 +8,8 @@ F:	configs/T1024RDB_NAND_defconfig
 F:	configs/T1024RDB_SDCARD_defconfig
 F:	configs/T1024RDB_SPIFLASH_defconfig
 F:	configs/T1024RDB_SECURE_BOOT_defconfig
+F:	configs/T1023RDB_defconfig
+F:	configs/T1023RDB_NAND_defconfig
+F:	configs/T1023RDB_SDCARD_defconfig
+F:	configs/T1023RDB_SPIFLASH_defconfig
+F:	configs/T1023RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index a0cf8f6fbf..052006610e 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
 obj-y   += t102xrdb.o
-obj-y   += cpld.o
+obj-$(CONFIG_T1024RDB)   += cpld.o
 obj-y   += eth_t102xrdb.o
 obj-$(CONFIG_PCI)       += pci.o
 endif
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index 2b17f50bae..922450e3c7 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -98,6 +98,30 @@ T1024RDB board Overview
      - Four I2C ports
 
 
+T1023RDB board Overview
+-----------------------
+- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
+- CoreNet fabric supporting coherent and noncoherent transactions with
+  prioritization and bandwidth allocation
+- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
+- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
+- Ethernet interfaces:
+  - one 1G RGMII port on-board(RTL8211FS PHY)
+  - one 1G SGMII port on-board(RTL8211FS PHY)
+  - one 2.5G SGMII port on-board(AQR105 PHY)
+- PCIe: Two Mini-PCIe connectors on-board.
+- SerDes: 4 lanes up to 10.3125GHz
+- NOR:  128MB S29GL01GS110TFIV10 Spansion NOR Flash
+- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
+- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
+- USB: one Type-A USB 2.0 port with internal PHY
+- eSDHC: support SD/MMC and eMMC card
+- 256Kbit M24256 I2C EEPROM
+- RTC: Real-time clock DS1339U on I2C bus
+- UART: one serial port on-board with RJ45 connector
+- Debugging: JTAG/COP for T1023 debugging
+
+
 Memory map on T1024RDB
 ----------------------
 Start Address  End Address      Description			Size
@@ -117,29 +141,39 @@ Start Address  End Address      Description			Size
 0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
 
 
-128MB NOR Flash memory Map
---------------------------
+128MB NOR Flash Memory Layout
+-----------------------------
 Start Address   End Address     Definition			Max size
 0xEFF40000      0xEFFFFFFF      u-boot (current bank)		768KB
 0xEFF20000      0xEFF3FFFF      u-boot env (current bank)	128KB
 0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)	128KB
 0xEFE00000      0xEFE3FFFF      QE firmware (current bank)	256KB
-0xED300000      0xEFEFFFFF      rootfs (alt bank)		44MB
+0xED300000      0xEFDFFFFF      rootfs (alt bank)		44MB
+0xED000000      0xED2FFFFF      Guest image #3 (alternate bank) 3MB
+0xECD00000      0xECFFFFFF      Guest image #2 (alternate bank) 3MB
+0xECA00000	0xECCFFFFF	Guest image #1 (alternate bank) 3MB
+0xEC900000	0xEC9FFFFF	HV config device tree(alt bank)	1MB
 0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank) 1MB
-0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)		7MB + 875KB
+0xEC700000	0xEC7FFFFF	HV.uImage (alternate bank)	1MB
+0xEC020000      0xEC6FFFFF      Linux.uImage (alt bank)		~7MB
 0xEC000000      0xEC01FFFF      RCW (alt bank)			128KB
 0xEBF40000      0xEBFFFFFF      u-boot (alt bank)		768KB
 0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)		128KB
 0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)		128KB
 0xEBE00000      0xEBE3FFFF      QE firmware (alt bank)		256KB
-0xE9300000      0xEBEFFFFF      rootfs (current bank)		44MB
+0xE9300000      0xEBDFFFFF      rootfs (current bank)		44MB
+0xE9000000      0xE92FFFFF      Guest image #3 (current bank)   3MB
+0xE8D00000      0xE8FFFFFF      Guest image #2 (current bank)   3MB
+0xE8A00000	0xE8CFFFFF	Guest image #1 (current bank)	3MB
+0xE8900000	0xE89FFFFF	HV config device tree(cur bank) 1MB
 0xE8800000      0xE88FFFFF      Hardware device tree (cur bank) 1MB
-0xE8020000      0xE86FFFFF      Linux.uImage (current bank)	7MB + 875KB
+0xE8700000	0xE87FFFFF	HV.uImage (current bank)	1MB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)	~7MB
 0xE8000000      0xE801FFFF      RCW (current bank)		128KB
 
 
-T1024 Clock frequency
----------------------
+T1024/T1023 Clock frequency
+---------------------------
 BIN   Core     DDR       Platform  FMan
 Bin1: 1400MHz  1600MT/s  400MHz    700MHz
 Bin2: 1200MHz  1600MT/s  400MHz    600MHz
@@ -155,16 +189,27 @@ Software configurations and board settings
    b. program u-boot.bin image to NOR flash
 	=> tftp 1000000 u-boot.bin
 	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
-	set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+	on T1024RDB:
+	   set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+	on T1023RDB:
+	   set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
 
    Switching between default bank0 and alternate bank4 on NOR flash
    To change boot source to vbank4:
-        via software:   run command 'cpld reset altbank' in u-boot.
-        via DIP-switch: set SW3[5:7] = '100'
+   on T1024RDB:
+	via software:   run command 'cpld reset altbank' in u-boot.
+	via DIP-switch: set SW3[5:7] = '100'
+   on T1023RDB:
+	via software:   run command 'gpio vbank4' in u-boot.
+	via DIP-switch: set SW3[5:7] = '100'
 
    To change boot source to vbank0:
-        via software:   run command 'cpld reset' in u-boot.
-        via DIP-Switch: set SW3[5:7] = '000'
+   on T1024RDB:
+	via software:   run command 'cpld reset' in u-boot.
+	via DIP-Switch: set SW3[5:7] = '000'
+   on T1023RDB:
+	via software:   run command 'gpio vbank0' in u-boot.
+	via DIP-switch: set SW3[5:7] = '000'
 
 2. NAND Boot:
    a. build PBL image for NAND boot
@@ -183,8 +228,11 @@ Software configurations and board settings
    b. program u-boot-with-spl-pbl.bin to SPI flash
 	=> tftp 1000000 u-boot-with-spl-pbl.bin
 	=> sf probe 0
-	=> sf erase 0 f0000
+	=> sf erase 0 100000
 	=> sf write 1000000 0 $filesize
+	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+	=> sf erase 100000 100000
+	=> sf write 1000000 110000 20000
 	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
 
 4. SD Boot:
@@ -236,23 +284,34 @@ Start		End		Definition	Size
 0x200000	0x27FFFF	QE Firmware	512KB(1 block)
 
 
+NAND Flash memory Map on T1023RDB
+----------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	u-boot		1MB
+0x100000	0x15FFFF	u-boot env	8KB
+0x160000	0x17FFFF	FMAN Ucode	128KB
+
+
 SD Card memory Map on T1024RDB
 ----------------------------------------------------
 Block		#blocks		Definition	Size
 0x008		2048		u-boot img	1MB
 0x800		0016		u-boot env	8KB
 0x820		0256		FMAN Ucode	128KB
-0x920		0256		QE Firmware	128KB
+0x920		0256		QE Firmware	128KB(only T1024RDB)
 
 
-SPI Flash memory Map on T1024RDB
+64MB SPI Flash memory Map on T102xRDB
 ----------------------------------------------------
 Start		End		Definition	Size
 0x000000	0x0FFFFF	u-boot img	1MB
 0x100000	0x101FFF	u-boot env	8KB
 0x110000	0x12FFFF	FMAN Ucode	128KB
-0x130000	0x14FFFF	QE Firmware	128KB
+0x130000	0x14FFFF	QE Firmware	128KB(only T1024RDB)
+0x300000	0x3FFFFF	device tree	128KB
+0x400000	0x9FFFFF	Linux kernel    6MB
+0xa00000	0x3FFFFFF	rootfs		54MB
 
 
-For more details, please refer to T1024RDB Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+For more details, please refer to T1024RDB Reference Manual
+and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a2a8f4ccf0..adf9fd5f78 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -135,8 +135,83 @@ found:
 	/* for DDR bus 32bit test on T1024 */
 	popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 #endif
+
+#ifdef CONFIG_T1023RDB
+	popts->wrlvl_ctl_2 = 0x07070606;
+	popts->half_strength_driver_enable = 1;
+#endif
 }
 
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 0x80000000,
+	.capacity = 0x80000000,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.bank_addr_bits = 2,
+	.bank_group_bits = 2,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 938,
+	.tckmax_ps = 1500,
+	.caslat_x = 0x000DFA00,
+	.taa_ps = 13500,
+	.trcd_ps = 13500,
+	.trp_ps = 13500,
+	.tras_ps = 33000,
+	.trc_ps = 46500,
+	.trfc1_ps = 260000,
+	.trfc2_ps = 160000,
+	.trfc4_ps = 110000,
+	.tfaw_ps = 25000,
+	.trrds_ps = 3700,
+	.trrdl_ps = 5300,
+	.tccdl_ps = 5355,
+	.refresh_rate_ps = 7800000,
+	.dq_mapping[0] = 0x0,
+	.dq_mapping[1] = 0x0,
+	.dq_mapping[2] = 0x0,
+	.dq_mapping[3] = 0x0,
+	.dq_mapping[4] = 0x0,
+	.dq_mapping[5] = 0x0,
+	.dq_mapping[6] = 0x0,
+	.dq_mapping[7] = 0x0,
+	.dq_mapping[8] = 0x0,
+	.dq_mapping[9] = 0x0,
+	.dq_mapping[10] = 0x0,
+	.dq_mapping[11] = 0x0,
+	.dq_mapping[12] = 0x0,
+	.dq_mapping[13] = 0x0,
+	.dq_mapping[14] = 0x0,
+	.dq_mapping[15] = 0x0,
+	.dq_mapping[16] = 0x0,
+	.dq_mapping[17] = 0x0,
+	.dq_mapping_ors = 1,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR4 on board";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+	    ((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_DEEP_SLEEP)
 void board_mem_sleep_setup(void)
 {
@@ -155,8 +230,9 @@ phys_size_t initdram(int board_type)
 	phys_size_t dram_size;
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
 	puts("Initializing....using SPD\n");
-
+#endif
 	dram_size = fsl_ddr_sdram();
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index f611ff07e9..856ec6e227 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -1,6 +1,8 @@
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
@@ -56,6 +58,7 @@ int board_eth_init(bd_t *bis)
 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
 	switch (srds_s1) {
+#ifdef CONFIG_T1024RDB
 	case 0x95:
 		/* set the on-board RGMII2  PHY */
 		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -63,10 +66,17 @@ int board_eth_init(bd_t *bis)
 		/* set 10G XFI with Aquantia AQR105 PHY */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		break;
+#endif
+	case 0x6a:
+	case 0x6b:
 	case 0x77:
 	case 0x135:
 		/* set the on-board 2.5G SGMII AQR105 PHY */
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
+#ifdef CONFIG_T1023RDB
+		/* set the on-board 1G SGMII RTL8211F PHY */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
+#endif
 		break;
 	default:
 		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
@@ -81,6 +91,14 @@ int board_eth_init(bd_t *bis)
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
+		case PHY_INTERFACE_MODE_SGMII:
+#if defined(CONFIG_T1023RDB)
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+#elif defined(CONFIG_T1024RDB)
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+#endif
+			fm_info_set_mdio(i, dev);
+			break;
 		case PHY_INTERFACE_MODE_SGMII_2500:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
@@ -110,13 +128,16 @@ int board_eth_init(bd_t *bis)
 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			      enum fm_port port, int offset)
 {
-	if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
-	    (port == FM1_DTSEC3)) {
+#if defined(CONFIG_T1024RDB)
+	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
+			(port == FM1_DTSEC3)) {
 		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
-		fdt_setprop(fdt, offset, "phy-connection-type",
-			    "sgmii-2500", 10);
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "sgmii-2500");
 		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
 	}
+#endif
 }
 
 void fdt_fixup_board_enet(void *fdt)
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg
new file mode 100644
index 0000000000..fa781d61a5
--- /dev/null
+++ b/board/freescale/t102xrdb/t1023_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000e 00000000 00000000 00000000
+3b800003 00000012 e8104000 21000000
+00000000 00000000 00000000 00020800
+00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index e196f12ac7..f971976d73 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -18,11 +18,25 @@
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 #include "t102xrdb.h"
+#ifdef CONFIG_T1024RDB
 #include "cpld.h"
+#endif
 #include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_T1023RDB
+enum {
+	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
+	GPIO1_EMMC_SEL,
+	GPIO1_VBANK0,
+	GPIO1_VBANK4    = 0x00008000, /* GPIO1_16/20/22,  100:vBank4 */
+	GPIO1_VBANK_MASK = 0x00008a00,
+	GPIO1_DIR_OUTPUT = 0x00028a00,
+	GPIO1_GET_VAL,
+};
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -34,14 +48,17 @@ int checkboard(void)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	printf("Board: %sRDB, ", cpu->name);
-	printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+#ifdef CONFIG_T1024RDB
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+#endif
+	printf("boot from ");
 
 #ifdef CONFIG_SDCARD
 	puts("SD/MMC\n");
 #elif CONFIG_SPIFLASH
 	puts("SPI\n");
-#else
+#elif defined(CONFIG_T1024RDB)
 	u8 reg;
 
 	reg = CPLD_READ(flash_csr);
@@ -52,17 +69,25 @@ int checkboard(void)
 		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
 		printf("NOR vBank%d\n", reg);
 	}
+#elif defined(CONFIG_T1023RDB)
+#ifdef CONFIG_NAND
+	puts("NAND\n");
+#else
+	printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
+	       GPIO1_VBANK4) >> 15 ? 4 : 0);
+#endif
 #endif
 
 	puts("SERDES Reference Clocks:\n");
 	if (srds_s1 == 0x95)
 		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
 	else
-		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
 
 	return 0;
 }
 
+#ifdef CONFIG_T1024RDB
 static void board_mux_lane(void)
 {
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -82,6 +107,7 @@ static void board_mux_lane(void)
 	}
 	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
 }
+#endif
 
 int board_early_init_f(void)
 {
@@ -124,7 +150,9 @@ int board_early_init_r(void)
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	setup_portals();
 #endif
+#ifdef CONFIG_T1024RDB
 	board_mux_lane();
+#endif
 
 	return 0;
 }
@@ -170,3 +198,62 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
+
+
+#ifdef CONFIG_T1023RDB
+static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 gpioval;
+
+	setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
+	gpioval = in_be32(&pgpio->gpdat);
+
+	switch (ctrl_type) {
+	case GPIO1_SD_SEL:
+		gpioval |= GPIO1_SD_SEL;
+		break;
+	case GPIO1_EMMC_SEL:
+		gpioval &= ~GPIO1_SD_SEL;
+		break;
+	case GPIO1_VBANK0:
+		gpioval &= ~GPIO1_VBANK_MASK;
+		break;
+	case GPIO1_VBANK4:
+		gpioval &= ~GPIO1_VBANK_MASK;
+		gpioval |= GPIO1_VBANK4;
+		break;
+	case GPIO1_GET_VAL:
+		return gpioval;
+	default:
+		break;
+	}
+	out_be32(&pgpio->gpdat, gpioval);
+
+	return 0;
+}
+
+static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+		    char * const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (!strcmp(argv[1], "vbank0"))
+		t1023rdb_gpio_ctrl(GPIO1_VBANK0);
+	else if (!strcmp(argv[1], "vbank4"))
+		t1023rdb_gpio_ctrl(GPIO1_VBANK4);
+	else if (!strcmp(argv[1], "sd"))
+		t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
+	else if (!strcmp(argv[1], "EMMC"))
+		t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
+	else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+U_BOOT_CMD(
+	gpio, 2, 0, gpio_cmd,
+	"for vbank0/vbank4/SD/eMMC switch control in runtime",
+	"command (e.g. gpio vbank4)"
+);
+#endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
index 2f23579b8f..3f5d85aa82 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -9,5 +9,7 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
-
+#ifdef CONFIG_T1023RDB
+static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
+#endif
 #endif
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 3f1533888d..9bd5247563 100644
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_LBMAP_RESET	0xFF
 #define CPLD_LBMAP_SHIFT	0x03
 #define CPLD_BOOT_SEL		0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST	0x04
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
index 59025eaf1e..8096ff9f37 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -10,7 +10,10 @@ aa55aa55 010e0100
 
 #For T2080 v1.1
 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
-1206001b 15000000 00000000 00000000
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
 66150002 00000000 e8104000 c1000000
 00800000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index ad393dfc5c..0c2c1c565b 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
 
 int misc_init_r(void)
 {
+	u8 reg;
+
+	/* Reset CS4315 PHY */
+	reg = CPLD_READ(reset_ctl);
+	reg |= CPLD_RSTCON_EDC_RST;
+	CPLD_WRITE(reset_ctl, reg);
+
 	return 0;
 }
 
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
index ab34b9ef4c..27a64b64b9 100644
--- a/board/freescale/t4qds/Kconfig
+++ b/board/freescale/t4qds/Kconfig
@@ -1,16 +1,3 @@
-if TARGET_T4240EMU
-
-config SYS_BOARD
-	default "t4qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "T4240EMU"
-
-endif
-
 if TARGET_T4240QDS
 
 config SYS_BOARD
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
index f88ee7df9e..b159113642 100644
--- a/board/freescale/t4qds/MAINTAINERS
+++ b/board/freescale/t4qds/MAINTAINERS
@@ -1,16 +1,14 @@
 T4QDS BOARD
-#M:	-
+M:	Shaohui Xie <Shaohui.Xie@freescale.com>
 S:	Maintained
 F:	board/freescale/t4qds/
 F:	include/configs/T4240QDS.h
 F:	configs/T4160QDS_defconfig
 F:	configs/T4160QDS_NAND_defconfig
 F:	configs/T4160QDS_SDCARD_defconfig
-F:	configs/T4160QDS_SPIFLASH_defconfig
 F:	configs/T4240QDS_defconfig
 F:	configs/T4240QDS_NAND_defconfig
 F:	configs/T4240QDS_SDCARD_defconfig
-F:	configs/T4240QDS_SPIFLASH_defconfig
 F:	configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
 
 T4160QDS_SECURE_BOOT BOARD
@@ -18,9 +16,3 @@ M:	Aneesh Bansal <aneesh.bansal@freescale.com>
 S:	Maintained
 F:	configs/T4160QDS_SECURE_BOOT_defconfig
 F:	configs/T4240QDS_SECURE_BOOT_defconfig
-
-T4240EMU BOARD
-M:	York Sun <yorksun@freescale.com>
-S:	Maintained
-F:	include/configs/T4240EMU.h
-F:	configs/T4240EMU_defconfig
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 4e8e5cb8e9..bd2c1f1622 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
 obj-$(CONFIG_T4240QDS) += t4240qds.o
-obj-$(CONFIG_T4240EMU) += t4240emu.o
 obj-$(CONFIG_T4240QDS)+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 8183af78fe..4d0e3c497d 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -25,7 +25,6 @@ struct board_specific_parameters {
  * for each n_ranks group.
  */
 
-#ifdef CONFIG_T4240QDS
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
@@ -63,31 +62,6 @@ static const struct board_specific_parameters rdimm0[] = {
 	{}
 };
 
-#else	/* CONFIG_T4240EMU */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
-	{}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{4,  2140, 0, 5,     8, 0x0, 0x0,   0xff,    2,  0},
-	{2,  2140, 0, 5,     8, 0x0, 0x0,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
-	{}
-};
-#endif	/* CONFIG_T4240EMU */
-
 /*
  * The three slots have slightly different timing. The center values are good
  * for all slots. We use identical speed tables for them. In future use, if
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6f09a7bba2..267494c8b3 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_27_5_11
-16070019 18101916 00000000 00000000
+1607001b 18101b16 00000000 00000000
 04362858 30548c00 ec020000 f5000000
 00000000 ee0000ee 00000000 000307fc
 00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
index 845c1b6d66..53ccabc0fb 100644
--- a/board/freescale/t4rdb/MAINTAINERS
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/freescale/t4rdb/
 F:	include/configs/T4240RDB.h
 F:	configs/T4160RDB_defconfig
 F:	configs/T4240RDB_defconfig
+F:	configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 3886e3ded1..83b55ee193 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T4240RDB) += t4240rdb.o
 obj-y	+= cpld.o
-obj-y	+= ddr.o
 obj-y	+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
+endif
+obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 5a43c1bc78..27b37b5cc4 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -108,11 +108,15 @@ phys_size_t initdram(int board_type)
 
 	puts("Initializing....using SPD\n");
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size = fsl_ddr_sdram_size();
+#endif
 
-	puts("    DDR: ");
 	return dram_size;
 }
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
new file mode 100644
index 0000000000..68ecde7909
--- /dev/null
+++ b/board/freescale/t4rdb/spl.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+
+#include "t4rdb.h"
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nSD boot...\n");
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	bd_t *bd;
+
+	bd = (bd_t *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+
+	mmc_boot();
+}
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
index c9f8ced2a3..e7bb673e46 100644
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ b/board/freescale/t4rdb/t4_pbi.cfg
@@ -19,9 +19,6 @@
 09000d00 00000000
 09000d04 fff80000
 09000d08 81000012
-#slow mdio clock
-095fc030 00008148
-095fd030 00808148
 #Configure alternate space
 09000010 00000000
 09000014 ff000000
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index e46c7b25a5..282fea4824 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -2,6 +2,6 @@
 aa55aa55 010e0100
 #serdes protocol  27_55_1_9
 16070019 18101916 00000000 00000000
-6c6e0848 00448c00 6c020000 f5000000
-00000000 ee0000ee 00000000 000287fc
-00000000 50000000 00000000 00000028
+6c6e0848 00448c00 ec020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index 474301e2a7..6a6b4b5cc1 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -51,6 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -91,6 +92,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
+
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -111,6 +114,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 18, BOOKE_PAGESZ_2G, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);