Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2

63 files changed, 1356 insertions, 358 deletions

diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 4a86d3c552..79fb71dc70 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -263,7 +263,6 @@ static void ft_blob_update(void *blob, bd_t *bd)
 {
 	int len, ret, nodeoffset = 0;
 	char module_name[MODULE_NAME_MAXLEN] = {0};
-	ulong memory_data[2] = {0};
 
 	compose_module_name(hw_id, module_name);
 	len = strlen(module_name) + 1;
@@ -273,22 +272,12 @@ static void ft_blob_update(void *blob, bd_t *bd)
 	printf("ft_blob_update(): cannot set /model property err:%s\n",
 		fdt_strerror(ret));
 
-	memory_data[0] = cpu_to_be32(bd->bi_memstart);
-	memory_data[1] = cpu_to_be32(bd->bi_memsize);
+	ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
-	nodeoffset = fdt_path_offset (blob, "/memory");
-	if (nodeoffset >= 0) {
-		ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
-					sizeof(memory_data));
-	if (ret < 0)
+	if (ret < 0) {
 		printf("ft_blob_update): cannot set /memory/reg "
 			"property err:%s\n", fdt_strerror(ret));
 	}
-	else {
-		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /memory node "
-		"err:%s\n", fdt_strerror(nodeoffset));
-	}
 }
 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
 
diff --git a/board/cds/common/cadmus.c b/board/freescale/common/cadmus.c
index 5f86de5af2..5f86de5af2 100644
--- a/board/cds/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
diff --git a/board/cds/common/cadmus.h b/board/freescale/common/cadmus.h
index 217ea64251..217ea64251 100644
--- a/board/cds/common/cadmus.h
+++ b/board/freescale/common/cadmus.h
diff --git a/board/cds/common/eeprom.c b/board/freescale/common/eeprom.c
index 5034e0ca2e..5034e0ca2e 100644
--- a/board/cds/common/eeprom.c
+++ b/board/freescale/common/eeprom.c
diff --git a/board/cds/common/eeprom.h b/board/freescale/common/eeprom.h
index 12a0789049..12a0789049 100644
--- a/board/cds/common/eeprom.h
+++ b/board/freescale/common/eeprom.h
diff --git a/board/cds/common/ft_board.c b/board/freescale/common/ft_board.c
index 3eda1009ef..6f221aff26 100644
--- a/board/cds/common/ft_board.c
+++ b/board/freescale/common/ft_board.c
@@ -21,24 +21,29 @@
  */
 
 #include <common.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 #include "cadmus.h"
 
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
+#if defined(CONFIG_OF_BOARD_SETUP)
 static void cds_pci_fixup(void *blob)
 {
-	int len;
-	u32 *map;
-	int slot;
-	int i;
+	int node, tmp[2];
+	const char *path;
+	int len, slot, i;
+	u32 *map = NULL;
 
-	map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
-
-	if (!map)
-		map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			node = fdt_path_offset(blob, path);
+			if (node >= 0) {
+				map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+			}
+		}
+	}
 
 	if (map) {
 		len /= sizeof(u32);
@@ -50,33 +55,18 @@ static void cds_pci_fixup(void *blob)
 			 * changes depending on the slot the carrier card is in.
 			 */
 			map[3] = ((map[3] + slot - 2) % 4) + 1;
-
 			map+=7;
 		}
-	} else {
-		printf("*** Warning - No PCI node found\n");
 	}
 }
-#endif
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
-
+	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
-
 	cds_pci_fixup(blob);
+#endif
 }
 #endif
diff --git a/board/cds/common/via.c b/board/freescale/common/via.c
index 4a63d77944..4a63d77944 100644
--- a/board/cds/common/via.c
+++ b/board/freescale/common/via.c
diff --git a/board/cds/common/via.h b/board/freescale/common/via.h
index 77cfacc526..77cfacc526 100644
--- a/board/cds/common/via.h
+++ b/board/freescale/common/via.h
diff --git a/board/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
index 29136508f5..29136508f5 100644
--- a/board/mpc8540ads/Makefile
+++ b/board/freescale/mpc8540ads/Makefile
diff --git a/board/mpc8540ads/config.mk b/board/freescale/mpc8540ads/config.mk
index 92f8931979..92f8931979 100644
--- a/board/mpc8540ads/config.mk
+++ b/board/freescale/mpc8540ads/config.mk
diff --git a/board/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S
index 544fde94c4..544fde94c4 100644
--- a/board/mpc8540ads/init.S
+++ b/board/freescale/mpc8540ads/init.S
diff --git a/board/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 914e51a760..35f5eeaf03 100644
--- a/board/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -30,11 +30,8 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <spd.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -77,13 +74,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    uint temp_ddrdll = 0;
 
 	    /*
@@ -125,9 +121,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -186,8 +181,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
@@ -282,8 +276,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
@@ -331,22 +324,25 @@ pci_init_board(void)
 }
 
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
 	ft_cpu_setup(blob, bd);
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
 	}
 }
 #endif
diff --git a/board/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
index e7a88cfa44..a7c68b3648 100644
--- a/board/mpc8540ads/u-boot.lds
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/mpc8540ads/init.o (.bootpg)
+    board/freescale/mpc8540ads/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/mpc8540ads/init.o (.text)
+    board/freescale/mpc8540ads/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/cds/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
index 7f53098850..7f53098850 100644
--- a/board/cds/mpc8541cds/Makefile
+++ b/board/freescale/mpc8541cds/Makefile
diff --git a/board/cds/mpc8541cds/config.mk b/board/freescale/mpc8541cds/config.mk
index 17cc8bce9c..17cc8bce9c 100644
--- a/board/cds/mpc8541cds/config.mk
+++ b/board/freescale/mpc8541cds/config.mk
diff --git a/board/cds/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S
index 978bda5e4d..978bda5e4d 100644
--- a/board/cds/mpc8541cds/init.S
+++ b/board/freescale/mpc8541cds/init.S
diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 558ba9903c..9ab98d4b68 100644
--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -28,6 +28,8 @@
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -203,8 +205,7 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -250,7 +251,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -263,7 +263,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -293,9 +293,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -344,8 +343,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
@@ -506,3 +504,31 @@ pci_init_board(void)
 	pci_mpc85xx_init(hose);
 #endif
 }
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
index de0923a0d8..4360d677ec 100644
--- a/board/cds/mpc8555cds/u-boot.lds
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/cds/mpc8555cds/init.o (.bootpg)
+    board/freescale/mpc8541cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/cds/mpc8555cds/init.o (.text)
+    board/freescale/mpc8541cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 68ccba746b..084d4b80d9 100644
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -27,13 +27,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCIE1	0x00200000
-#define LAWAR_TRGT_PCIE2	0x00100000
-#define LAWAR_TRGT_PCIE3	0x00300000
-#define LAWAR_TRGT_LBC		0x00400000
-#define LAWAR_TRGT_DDR		0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -212,31 +205,31 @@ law_entry:
 	.long (4f-3f)/8
 3:
 	.long	0
-	.long	(LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+	.long	(LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
 	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	.long	(CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCIE2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	/* contains both PCIE3 MEM & IO space */
 	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
 	entry_end
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index b6c9e93d50..66cb536a4b 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -29,14 +29,11 @@
 #include <asm/io.h>
 #include <spd.h>
 #include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/pixis.h"
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -52,10 +49,9 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %x\n",&gur->porpllsr);
@@ -149,8 +145,7 @@ int first_free_busno=0;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy)
 	return val;
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
+
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
 	ft_cpu_setup(blob, bd);
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
 #ifdef CONFIG_PCI1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
-#endif
-#ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
-		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCIE2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
-		debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_PCIE1
+		path = fdt_getprop(blob, node, "pci2", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCIE3
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
-		debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci3", NULL);
+		if (path) {
+			tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
+	}
 }
 #endif
diff --git a/board/cds/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
index 7f53098850..7f53098850 100644
--- a/board/cds/mpc8548cds/Makefile
+++ b/board/freescale/mpc8548cds/Makefile
diff --git a/board/cds/mpc8548cds/config.mk b/board/freescale/mpc8548cds/config.mk
index b23bc8737d..b23bc8737d 100644
--- a/board/cds/mpc8548cds/config.mk
+++ b/board/freescale/mpc8548cds/config.mk
diff --git a/board/cds/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
index 72940b0350..a83a0952c3 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/freescale/mpc8548cds/init.S
@@ -28,13 +28,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCI2		0x00100000
-#define LAWAR_TRGT_PCIE		0x00200000
-#define LAWAR_TRGT_RIO		0x00c00000
-#define LAWAR_TRGT_LBC		0x00400000
-#define LAWAR_TRGT_DDR		0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -232,39 +225,39 @@ law_entry:
 	.long (4f-3f)/8
 3:
 	.long  0
-	.long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+	.long  (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
 #ifdef CFG_PCI1_MEM_PHYS
 	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 #ifdef CFG_PCI2_MEM_PHYS
 	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 #ifdef CFG_PCIE1_MEM_PHYS
 	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 #endif
 
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 #ifdef CFG_RIO_MEM_PHYS
 	.long	(CFG_RIO_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
 #endif
 4:
 	entry_end
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 36d7e1ed48..47e2dd86cb 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -29,14 +29,13 @@
 #include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -55,9 +54,8 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -96,7 +94,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -109,7 +106,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -139,9 +136,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -177,8 +173,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
@@ -330,8 +325,7 @@ int first_free_busno=0;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 
@@ -524,30 +518,30 @@ int last_stage_init(void)
 }
 
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_pci_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
-
+	int node, tmp[2];
+	const char *path;
 
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
 #ifdef CONFIG_PCI1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
-
 #ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
-		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
+	}
 }
 #endif
diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
index b19c481a96..ee772d3ae2 100644
--- a/board/cds/mpc8548cds/u-boot.lds
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/cds/mpc8548cds/init.o (.bootpg)
+    board/freescale/mpc8548cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/cds/mpc8548cds/init.o (.text)
+    board/freescale/mpc8548cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/cds/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
index 7f53098850..7f53098850 100644
--- a/board/cds/mpc8555cds/Makefile
+++ b/board/freescale/mpc8555cds/Makefile
diff --git a/board/cds/mpc8555cds/config.mk b/board/freescale/mpc8555cds/config.mk
index 5dcaa774db..5dcaa774db 100644
--- a/board/cds/mpc8555cds/config.mk
+++ b/board/freescale/mpc8555cds/config.mk
diff --git a/board/cds/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S
index 978bda5e4d..978bda5e4d 100644
--- a/board/cds/mpc8555cds/init.S
+++ b/board/freescale/mpc8555cds/init.S
diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 8f1642187c..74c220d4fd 100644
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -26,6 +26,8 @@
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -201,8 +203,7 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -248,7 +249,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -261,7 +261,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -291,9 +291,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -342,8 +341,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
@@ -506,3 +504,31 @@ pci_init_board(void)
 	pci_mpc85xx_init(hose);
 #endif
 }
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose[0].last_busno - hose[0].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = hose[1].last_busno - hose[1].first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
index 7a5daefeb7..df21ea86e6 100644
--- a/board/cds/mpc8541cds/u-boot.lds
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/cds/mpc8541cds/init.o (.bootpg)
+    board/freescale/mpc8555cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +64,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/cds/mpc8541cds/init.o (.text)
+    board/freescale/mpc8555cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
index 29136508f5..29136508f5 100644
--- a/board/mpc8560ads/Makefile
+++ b/board/freescale/mpc8560ads/Makefile
diff --git a/board/mpc8560ads/config.mk b/board/freescale/mpc8560ads/config.mk
index 9aef2bb163..9aef2bb163 100644
--- a/board/mpc8560ads/config.mk
+++ b/board/freescale/mpc8560ads/config.mk
diff --git a/board/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S
index 544fde94c4..544fde94c4 100644
--- a/board/mpc8560ads/init.S
+++ b/board/freescale/mpc8560ads/init.S
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index eef524b45e..bb7f11bcc8 100644
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -32,10 +32,8 @@
 #include <ioports.h>
 #include <spd.h>
 #include <miiphy.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -278,13 +276,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    uint temp_ddrdll = 0;
 
 	    /*
@@ -326,9 +323,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -387,8 +383,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
@@ -483,8 +478,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
@@ -548,35 +542,25 @@ pci_init_board(void)
 }
 
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_soc_setup(void *blob, bd_t *bd)
-{
-	u32 *p;
-	int len;
-
-	p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
-
-	if (p != NULL)
-		*p = cpu_to_be32(bd->bi_brgfreq);
-
-	p = ft_get_prop(blob,
-			"/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
-			&len);
-	if (p != NULL)
-		*p = cpu_to_be32(bd->bi_baudrate);
-
-	p = ft_get_prop(blob,
-			"/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
-			&len);
-	if (p != NULL)
-		*p = cpu_to_be32(bd->bi_baudrate);
-}
-
+#if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
+	int node, tmp[2];
+	const char *path;
+
 	ft_cpu_setup(blob, bd);
-	ft_soc_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
 }
 #endif
diff --git a/board/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
index 726a153f98..c2cba617ea 100644
--- a/board/mpc8560ads/u-boot.lds
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/mpc8560ads/init.o (.bootpg)
+    board/freescale/mpc8560ads/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -65,7 +65,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/mpc8560ads/init.o (.text)
+    board/freescale/mpc8560ads/init.o (.text)
     cpu/mpc85xx/commproc.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
diff --git a/board/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
index a799aa4cc5..643fbc041d 100644
--- a/board/mpc8568mds/Makefile
+++ b/board/freescale/mpc8568mds/Makefile
@@ -29,9 +29,7 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o \
-	bcsr.o \
-	ft_board.o
+COBJS	:= $(BOARD).o bcsr.o
 
 SOBJS	:= init.o
 
diff --git a/board/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
index aae0f98e03..aae0f98e03 100644
--- a/board/mpc8568mds/bcsr.c
+++ b/board/freescale/mpc8568mds/bcsr.c
diff --git a/board/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
index aefd9bf54d..aefd9bf54d 100644
--- a/board/mpc8568mds/bcsr.h
+++ b/board/freescale/mpc8568mds/bcsr.h
diff --git a/board/mpc8568mds/config.mk b/board/freescale/mpc8568mds/config.mk
index 021522cafc..021522cafc 100644
--- a/board/mpc8568mds/config.mk
+++ b/board/freescale/mpc8568mds/config.mk
diff --git a/board/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
index 972a7d4299..e36036daf0 100644
--- a/board/mpc8568mds/init.S
+++ b/board/freescale/mpc8568mds/init.S
@@ -28,7 +28,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -216,15 +215,14 @@ tlb1_entry:
 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
 #define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
-#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
 #define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
-#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
+#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
 #define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
diff --git a/board/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 818ff138a9..460cb1b275 100644
--- a/board/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -26,9 +26,12 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <i2c.h>
 #include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "bcsr.h"
 
@@ -133,7 +136,6 @@ long int
 initdram(int board_type)
 {
 	long dram_size = 0;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
@@ -146,7 +148,7 @@ initdram(int board_type)
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -176,9 +178,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -211,8 +212,7 @@ sdram_init(void)
 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 
 	uint idx;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 
@@ -337,16 +337,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
 };
 #endif
 
-static struct pci_controller hose[] = {
-	{
+static struct pci_controller pci1_hose = {
 #ifndef CONFIG_PCI_PNP
 	config_table: pci_mpc8568mds_config_table,
 #endif
-	}
 };
-
 #endif	/* CONFIG_PCI */
 
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif  /* CONFIG_PCIE1 */
+
+int first_free_busno = 0;
+
 /*
  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
  */
@@ -389,11 +392,164 @@ pib_init(void)
 	asm("eieio");
 }
 
+#ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
-#ifdef CONFIG_PCI
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCI1
+{
 	pib_init();
-	pci_mpc85xx_init(hose);
+
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci1_hose;
+
+	uint pci_32 = 1;      /* PORDEVSR[15] */
+	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
+	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
+
+	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+	uint pci_speed = 66666000;
+
+	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter"
+			);
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+				CFG_PCI_MEMORY_BUS,
+				CFG_PCI_MEMORY_PHYS,
+				CFG_PCI_MEMORY_SIZE,
+				PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+				CFG_PCI1_MEM_BASE,
+				CFG_PCI1_MEM_PHYS,
+				CFG_PCI1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+				CFG_PCI1_IO_BASE,
+				CFG_PCI1_IO_PHYS,
+				CFG_PCI1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		first_free_busno = hose->last_busno+1;
+		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+	} else {
+	printf ("    PCI: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 #endif
+
+#ifdef CONFIG_PCIE1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pcie1_hose;
+	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+	int pcie_configured  = io_sel >= 1;
+
+	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n    PCIE connected to slot as %s (base address %x)",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
+		}
+		printf ("\n");
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+				CFG_PCI_MEMORY_BUS,
+				CFG_PCI_MEMORY_PHYS,
+				CFG_PCI_MEMORY_SIZE,
+				PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+				CFG_PCIE1_MEM_BASE,
+				CFG_PCIE1_MEM_PHYS,
+				CFG_PCIE1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+				CFG_PCIE1_IO_BASE,
+				CFG_PCIE1_IO_PHYS,
+				CFG_PCIE1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+
+		first_free_busno=hose->last_busno+1;
+
+	} else {
+		printf ("    PCIE: disabled\n");
+	}
 }
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	ft_cpu_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI1
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_PCIE1
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/board/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
index 71099f6f13..4682041ad7 100644
--- a/board/mpc8568mds/u-boot.lds
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -37,7 +37,7 @@ SECTIONS
   .bootpg 0xFFFFF000:
   {
 	cpu/mpc85xx/start.o	(.bootpg)
-	board/mpc8568mds/init.o (.bootpg)
+	board/freescale/mpc8568mds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -67,7 +67,7 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/mpc8568mds/init.o (.text)
+    board/freescale/mpc8568mds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
index b05424d32b..7176770f68 100644
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -329,25 +329,14 @@ nand_init (void)
  */
 void ft_blob_update(void *blob, bd_t *bd)
 {
-	int ret, nodeoffset = 0;
-	ulong memory_data[2] = {0};
+	int ret;
 
-	memory_data[0] = cpu_to_be32(bd->bi_memstart);
-	memory_data[1] = cpu_to_be32(bd->bi_memsize);
+	ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
-	nodeoffset = fdt_find_node_by_path (blob, "/memory");
-	if (nodeoffset >= 0) {
-		ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
-					sizeof(memory_data));
-	if (ret < 0)
+	if (ret < 0) {
 		printf("ft_blob_update): cannot set /memory/reg "
 			"property err:%s\n", fdt_strerror(ret));
 	}
-	else {
-		/* memory node is required in dts */
-		printf("ft_blob_update(): cannot find /memory node "
-		"err:%s\n", fdt_strerror(nodeoffset));
-	}
 }
 
 void ft_board_setup(void *blob, bd_t *bd)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 3b3c8ed26d..64dfe0930c 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -35,8 +35,7 @@ long int fixed_sdram (void);
 int board_pre_init (void)
 {
 #if defined(CONFIG_PCI)
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile ccsr_pcix_t *pci = &immr->im_pcix;
+	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
 	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -68,14 +67,13 @@ long int initdram (int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur= &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 #endif
 
 #if defined(CONFIG_DDR_DLL)
@@ -138,8 +136,7 @@ long int initdram (int board_type)
 		 * enable errors */
 		uint *p = 0;
 		uint i = 0;
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 		dma_init();
 		for (*p = 0; p < (uint *)(8 * 1024); p++) {
 			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -222,8 +219,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
 #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile
new file mode 100644
index 0000000000..6dec0136c2
--- /dev/null
+++ b/board/ms7722se/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7722se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ms7722se/config.mk b/board/ms7722se/config.mk
new file mode 100644
index 0000000000..4797d6f8f6
--- /dev/null
+++ b/board/ms7722se/config.mk
@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
new file mode 100644
index 0000000000..2024e27ffe
--- /dev/null
+++ b/board/ms7722se/lowlevel_init.S
@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ *  Board specific low level init code, called _very_ early in the
+ *  startup sequence. Relocation to SDRAM has not happened yet, no
+ *  stack is available, bss section has not been initialised, etc.
+ *
+ *  (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	mov.l	CCR_A, r1	! Address of Cache Control Register
+	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	mov.l	r0, @r1
+
+	mov.l	MMUCR_A, r1	! Address of MMU Control Register
+	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
+	mov.l	MSTPCR0_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
+	mov.l	MSTPCR2_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	SBSCR_A, r1	!
+	mov.w	SBSCR_D, r0	!
+	mov.w	r0, @r1
+
+	mov.l	PSCR_A, r1	!
+	mov.w	PSCR_D, r0	!
+	mov.w	r0, @r1
+
+!	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+!	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+!	mov.w	r0, @r1
+
+	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
+	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	mov.w	r0, @r1
+
+	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	mov.l	FRQCR_D, r0	!
+	mov.l	r0, @r1
+
+	mov.l	CCR_A, r1		! Address of Cache Control Register
+	mov.l	CCR_D_2, r0	! ??
+	mov.l	r0, @r1
+
+bsc_init:
+
+	mov.l	PSELA_A, r1
+	mov.w	PSELA_D, r0
+	mov.w	r0, @r1
+
+	mov.l	DRVCR_A, r1
+	mov.w	DRVCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PCCR_A, r1
+	mov.w	PCCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PECR_A, r1
+	mov.w	PECR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PJCR_A, r1
+	mov.w	PJCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PXCR_A, r1
+	mov.w	PXCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	CMNCR_A, r1	! CMNCR address -> R1
+	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	r0, @r1		! CMNCR set
+
+	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
+	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	r0, @r1		! CS0BCR set
+
+	mov.l	CS2BCR_A, r1	! CS2BCR address -> R1
+	mov.l	CS2BCR_D, r0	! CS2BCR data    -> R0
+	mov.l	r0, @r1		! CS2BCR set
+
+	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
+	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
+	mov.l	r0, @r1		! CS4BCR set
+
+	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
+	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	r0, @r1		! CS5ABCR set
+
+	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
+	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	r0, @r1		! CS5BBCR set
+
+	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
+	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	r0, @r1		! CS6ABCR set
+
+	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
+	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	r0, @r1		! CS0WCR set
+
+	mov.l	CS2WCR_A, r1	! CS2WCR address -> R1
+	mov.l 	CS2WCR_D, r0	! CS2WCR data    -> R0
+	mov.l	r0, @r1		! CS2WCR set
+
+	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
+	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	r0, @r1		! CS4WCR set
+
+	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
+	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	r0, @r1		! CS5AWCR set
+
+	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
+	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	r0, @r1		! CS5BWCR set
+
+	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
+	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	r0, @r1		! CS6AWCR set
+
+	! SDRAM initialization
+	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
+	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
+	mov.l	r0, @r1		! SB_SDCR set
+
+	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
+	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
+	mov.l	r0, @r1		! SB_SDWCR set
+
+	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
+	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
+	mov.l	r0, @r1		! SB_SDPCR set
+
+	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
+	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
+	mov.l	r0, @r1		! SB_RTCOR set
+
+	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
+	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
+	mov.l	r0, @r1		! SB_RTCSR set
+
+	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
+	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov.b	r0, @r1		! SDMR3 set
+
+	! BL bit off (init = ON)  (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	mov	#0, r0
+
+	.align	2
+
+CCR_A:		.long	CCR
+MMUCR_A:	.long	MMUCR
+MSTPCR0_A:	.long	MSTPCR0
+MSTPCR2_A:	.long	MSTPCR2
+SBSCR_A:	.long	SBSCR
+PSCR_A:		.long	PSCR
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+
+CCR_D:		.long	0x00000800
+CCR_D_2:	.long	0x00000103
+MMUCR_D:	.long	0x00000004
+MSTPCR0_D:	.long	0x00001001
+MSTPCR2_D:	.long	0xffffffff
+FRQCR_D:	.long	0x07022538
+
+PSELA_A:	.long   0xa405014E
+PSELA_D:	.word   0x0A10
+	.align 2
+
+DRVCR_A:	.long   0xa405018A
+DRVCR_D:	.word   0x0554
+	.align 2
+
+PCCR_A:		.long   0xa4050104
+PCCR_D:		.word   0x8800
+	.align 2
+
+PECR_A:		.long   0xa4050108
+PECR_D:		.word   0x0000
+	.align 2
+
+PJCR_A:		.long   0xa4050110
+PJCR_D:		.word   0x1000
+	.align 2
+
+PXCR_A:		.long   0xa4050148
+PXCR_D:		.word   0x0AAA
+	.align 2
+
+CMNCR_A:	.long	CMNCR
+CMNCR_D:	.long	0x00000013
+CS0BCR_A:	.long	CS0BCR		! Flash bank 1
+CS0BCR_D:	.long	0x24920400
+CS2BCR_A:	.long	CS2BCR		! SRAM
+CS2BCR_D:	.long	0x24920400
+CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
+CS4BCR_D:	.long	0x24920400
+CS5ABCR_A:	.long	CS5ABCR		! Ext slot
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_A:	.long	CS5BBCR		! USB controller
+CS5BBCR_D:	.long	0x24920400
+CS6ABCR_A:	.long	CS6ABCR		! Ethernet
+CS6ABCR_D:	.long	0x24920400
+
+CS0WCR_A:	.long	CS0WCR
+CS0WCR_D:	.long	0x00000300
+CS2WCR_A:	.long	CS2WCR
+CS2WCR_D:	.long	0x00000300
+CS4WCR_A:	.long	CS4WCR
+CS4WCR_D:	.long	0x00000300
+CS5AWCR_A:	.long	CS5AWCR
+CS5AWCR_D:	.long	0x00000300
+CS5BWCR_A:	.long	CS5BWCR
+CS5BWCR_D:	.long	0x00000300
+CS6AWCR_A:	.long	CS6AWCR
+CS6AWCR_D:	.long	0x00000300
+
+SDCR_A:		.long	SBSC_SDCR
+SDCR_D:		.long	0x00020809
+SDWCR_A:	.long	SBSC_SDWCR
+SDWCR_D:	.long	0x00164d0d
+SDPCR_A:	.long	SBSC_SDPCR
+SDPCR_D:	.long	0x00000087
+RTCOR_A:	.long	SBSC_RTCOR
+RTCOR_D:	.long	0xA55A0034
+RTCSR_A:	.long	SBSC_RTCSR
+RTCSR_D:	.long	0xA55A0010
+SDMR3_A:	.long	0xFE500180
+
+	.align	1
+
+SBSCR_D:	.word	0x0040
+PSCR_D:		.word	0x0000
+RWTCSR_D_1:	.word	0xA507
+RWTCSR_D_2:	.word	0xA507
+RWTCNT_D:	.word	0x5A00
+
+SR_MASK_D:	.long	0xEFFFFF0F
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
new file mode 100644
index 0000000000..0d3d55cf5c
--- /dev/null
+++ b/board/ms7722se/ms7722se.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/ms7722se.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#define LED_BASE	0xB0800000
+
+int checkboard(void)
+{
+	puts("BOARD: Hitachi UL MS7722SE\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Setup PTXMD[1:0] for /CS6A */
+	outw(inw(PXCR) & ~0xf000, PXCR);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+	*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
+}
diff --git a/board/ms7722se/u-boot.lds b/board/ms7722se/u-boot.lds
new file mode 100644
index 0000000000..692bc62918
--- /dev/null
+++ b/board/ms7722se/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile
new file mode 100644
index 0000000000..f81d56cb44
--- /dev/null
+++ b/board/ms7750se/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7750se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+	$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
diff --git a/board/ms7750se/config.mk b/board/ms7750se/config.mk
new file mode 100644
index 0000000000..1eed5802e1
--- /dev/null
+++ b/board/ms7750se/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x8FFC0000
diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S
new file mode 100644
index 0000000000..d3e3cd5e8d
--- /dev/null
+++ b/board/ms7750se/lowlevel_init.S
@@ -0,0 +1,179 @@
+/*
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_CPU_SH7751
+#define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MARUBUN_PCCARD
+#define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#else /* CONFIG_MARUBUN_PCCARD */
+#define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#endif /* CONFIG_MARUBUN_PCCARD */
+#define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#else /* CONFIG_CPU_SH7751 */
+#define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
+#define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#endif /* CONFIG_CPU_SH7751 */
+
+	.global lowlevel_init
+	.text
+	.align  2
+
+lowlevel_init:
+
+	mov.l   CCR_A, r1               ! CCR Address
+	mov.l   CCR_D_DISABLE, r0       ! CCR Data
+	mov.l   r0, @r1
+
+init_bsc:
+	mov.l	FRQCR_A,r1	/* FRQCR Address */
+	mov.l	FRQCR_D,r0	/* FRQCR Data */
+	mov.w	r0,@r1
+
+	mov.l	BCR1_A,r1	/* BCR1 Address */
+	mov.l	BCR1_D,r0	/* BCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	BCR2_A,r1	/* BCR2 Address */
+	mov.l	BCR2_D,r0	/* BCR2 Data */
+	mov.w	r0,@r1
+
+	mov.l	WCR1_A,r1	/* WCR1 Address */
+	mov.l	WCR1_D,r0	/* WCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR2_A,r1	/* WCR2 Address */
+	mov.l	WCR2_D,r0	/* WCR2 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR3_A,r1	/* WCR3 Address */
+	mov.l	WCR3_D,r0	/* WCR3 Data */
+	mov.l	r0,@r1
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D1,r0	/* MCR Data1 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	! Do you need PCMCIA setting?
+	! If so, please add the lines here...
+
+	mov.l	RTCNT_A,r1	/* RTCNT Address */
+	mov.l	RTCNT_D,r0	/* RTCNT Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCOR_A,r1	/* RTCOR Address */
+	mov.l	RTCOR_D,r0	/* RTCOR Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCSR_A,r1	/* RTCSR Address */
+	mov.l	RTCSR_D,r0	/* RTCSR Data */
+	mov.w	r0,@r1
+
+	mov.l	RFCR_A,r1	/* RFCR Address */
+	mov.l	RFCR_D,r0	/* RFCR Data */
+	mov.w	r0,@r1		/* Clear reflesh counter */
+	/* Wait DRAM refresh 30 times */
+	mov	#30,r3
+1:
+	mov.w	@r1,r0
+	extu.w	r0,r2
+	cmp/hi	r3,r2
+	bf	1b
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D2,r0	/* MCR Data2 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	rts
+	 nop
+
+	.align	2
+
+CCR_A:          .long   CCR
+CCR_D_DISABLE:  .long   0x0808
+FRQCR_A:	.long	FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_TYPE_R
+		.long	0x00000e1a	/* 12:3:3 */
+#else	/* CONFIG_CPU_TYPE_R */
+#ifdef CONFIG_GOOD_SESH4
+		.long	0x00000e13	/* 6:2:1 */
+#else
+		.long	0x00000e23	/* 6:1:1 */
+#endif
+#endif	/* CONFIG_CPU_TYPE_R */
+
+BCR1_A:		.long	BCR1
+BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
+BCR2_A:		.long	BCR2
+BCR2_D:		.long	BCR2_D_VALUE	/* Bus width settings */
+WCR1_A:		.long	WCR1
+WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
+WCR2_A:		.long	WCR2
+WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
+WCR3_A:		.long	WCR3
+WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
+RTCSR_A:	.long	RTCSR
+RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
+RTCNT_A:	.long	RTCNT
+RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCOR_A:	.long	RTCOR
+RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+SDMR3_A:	.long	SDMR3_ADDRESS
+MCR_A:		.long	MCR
+MCR_D1:		.long	MCR_D1_VALUE
+MCR_D2:		.long	MCR_D2_VALUE
+RFCR_A:		.long	RFCR
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
diff --git a/board/mpc8568mds/ft_board.c b/board/ms7750se/ms7750se.c
index 36815ccfbb..d2d824c5a7 100644
--- a/board/mpc8568mds/ft_board.c
+++ b/board/ms7750se/ms7750se.c
@@ -1,5 +1,6 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor.
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -11,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,25 +22,30 @@
  */
 
 #include <common.h>
+#include <asm/processor.h>
 
-#include <ft_build.h>
+int checkboard(void)
+{
+	puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
 
-extern void ft_cpu_setup(void *blob, bd_t *bd);
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int board_late_init(void)
 {
-	u32 *p;
-	int len;
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
+	return 0;
 }
-#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */
diff --git a/board/ms7750se/u-boot.lds b/board/ms7750se/u-boot.lds
new file mode 100644
index 0000000000..692bc62918
--- /dev/null
+++ b/board/ms7750se/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 6ead1d0630..999d8b5259 100644
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -45,8 +45,7 @@ long int fixed_sdram(void);
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -79,13 +78,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    int i,x;
 
 	    x = 10;
@@ -133,9 +131,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -229,8 +226,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index a10075451e..bfde6959b4 100644
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -232,13 +232,12 @@ initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 	puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	    int i,x;
 
 	    x = 10;
@@ -287,9 +286,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -382,8 +380,7 @@ int testdram (void)
 long int fixed_sdram (void)
 {
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index e8b9929e77..47df884ce5 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -264,16 +263,15 @@ long int initdram (int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif
 #endif /* 0 */
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur= &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_DDR_DLL)
 	uint temp_ddrdll = 0;
@@ -336,8 +334,7 @@ long int initdram (int board_type)
 		 * enable errors */
 		uint *p = 0;
 		uint i = 0;
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 		dma_init();
 		for (*p = 0; p < (uint *)(8 * 1024); p++) {
 			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -424,8 +421,7 @@ long int fixed_sdram (void)
 #define CFG_DDR_CONTROL 0xc2000000
 
   #ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds		= 0x00000007;
 	ddr->cs1_bnds		= 0x0010001f;
diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c
index a58c043b62..3649acf07d 100644
--- a/board/stxgp3/stxgp3.c
+++ b/board/stxgp3/stxgp3.c
@@ -203,8 +203,7 @@ int
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -283,11 +282,10 @@ initdram (int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		uint temp_ddrdll = 0;
 
 		/* Work around to stabilize DDR DLL */
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 9bacb98d86..e2b38a6205 100644
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -252,8 +252,7 @@ int
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
-	volatile ccsr_pcix_t *pci = &immr->im_pcix;
+	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
 	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -302,8 +301,7 @@ initdram (int board_type)
 
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		uint temp_ddrdll = 0;
 
 		/* Work around to stabilize DDR DLL */
diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c
index 9c1f087687..2053adefb4 100644
--- a/board/tqm85xx/sdram.c
+++ b/board/tqm85xx/sdram.c
@@ -57,8 +57,7 @@ int cas_latency(void);
 long int sdram_setup(int casl)
 {
 	int i;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
 	unsigned long cfg_ddr_timing1;
 	unsigned long cfg_ddr_mode;
 
@@ -150,8 +149,7 @@ long int initdram (int board_type)
 	 * This DLL-Override only used on TQM8540 and TQM8560
 	 */
 	{
-		volatile immap_t *immap = (immap_t *) CFG_IMMR;
-		volatile ccsr_gur_t *gur= &immap->im_gur;
+		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 		int i,x;
 
 		x = 10;
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
index 256c076c7d..5d5cb1b75c 100644
--- a/board/tqm85xx/tqm85xx.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -262,8 +262,7 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	/*
 	 * Adjust flash start and offset to detected values
@@ -324,9 +323,8 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
index db0a7e5eb8..4342ebc841 100644
--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -33,6 +33,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
+
 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
     && !defined(CONFIG_TQM885D)
 # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
@@ -828,3 +830,5 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 
 /*-----------------------------------------------------------------------
  */
+
+#endif /* !defined(CFG_FLASH_CFI_DRIVER) */
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index cebdcc0764..fcd941e0d2 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFFFFF
 
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
 const uint sdram_table[] =
 {
 	/*
@@ -63,14 +64,14 @@ const uint sdram_table[] =
 	/*
 	 * Single Write. (Offset 18 in UPMA RAM)
 	 */
-	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+	0x1FF5FC47, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	/*
 	 * Burst Write. (Offset 20 in UPMA RAM)
 	 */
 	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
-					    _NOT_USED_,
+	0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	/*
@@ -83,7 +84,7 @@ const uint sdram_table[] =
 	/*
 	 * Exception. (Offset 3c in UPMA RAM)
 	 */
-	0x7FFFFC07, /* last */
+	0xFFFFFC07, /* last */
 		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
 };
 
@@ -183,7 +184,7 @@ long int initdram (int board_type)
 #ifndef	CONFIG_CAN_DRIVER
 	if ((board_type != 'L') &&
 	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
 		memctl->memc_or3 = CFG_OR3_PRELIM;
 		memctl->memc_br3 = CFG_BR3_PRELIM;
 	}
@@ -259,7 +260,7 @@ long int initdram (int board_type)
 #ifndef	CONFIG_CAN_DRIVER
 	if ((board_type != 'L') &&
 	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
 		/*
 		 * Check Bank 1 Memory Size
 		 * use current column settings