diff options
| author | Vignesh R <vigneshr@ti.com> | 2016-02-10 10:51:43 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-02-15 12:04:46 -0500 |
| commit | 900e2104d8d336d85d1a80e3906458ee318a3c0b (patch) | |
| tree | f2c2f4fc24919a4134e241dd1c9e958d68176208 /board | |
| parent | 195629cd5350419a04e8ac5d206c58714f9b4385 (diff) | |
| download | talos-obmc-uboot-900e2104d8d336d85d1a80e3906458ee318a3c0b.tar.gz talos-obmc-uboot-900e2104d8d336d85d1a80e3906458ee318a3c0b.zip | |
ARM : DRA7: Switch QSPI to use MODE-0 at 64MHz
According to Data Manual(SPRS915P) of AM572x, TI QSPI controller on
DRA74 EVM(rev 1.1+) can support up to 64MHz in MODE-0, whereas MODE-3 is
limited to 48MHz. Hence, switch to MODE-0 for better throughput.
Also, add IODelay parameters for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/dra7xx/mux_data.h | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 1bfb36243b..bec3b553bc 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -213,12 +213,12 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ - {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */ - {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */ - {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */ - {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */ - {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */ - {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ @@ -229,7 +229,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ - {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */ {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */ @@ -430,6 +430,14 @@ const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */ + {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */ + {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */ + {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */ + {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ }; const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { @@ -486,6 +494,14 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */ + {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */ + {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */ + {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ }; #endif |
