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authorPaul Burton <paul.burton@imgtec.com>2015-01-29 01:28:03 +0000
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2015-01-29 12:55:01 +0100
commit8755d50706742e4d302a335f4e69dd6430ec12a2 (patch)
treeb7730ef7f29fc91b729413d7f447075972f3a2f3 /board
parentdd7c72006e51f0d27e5cb1dcf60d5b9bf307565e (diff)
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MIPS: clear TagLo select 2 during cache init
Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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