sniper: Mux configuration cleanup

This cleans up the mux configuration a bit, setting mmc clock signals to input
enabled and specifying pull-down (0) when pull is not used.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

1 files changed, 37 insertions, 37 deletions

diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h
index b2a09b3cd0..e5d0774e78 100644
--- a/board/lge/sniper/sniper.h
+++ b/board/lge/sniper/sniper.h
@@ -51,13 +51,13 @@
 	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
 	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */ \
 	/* GPMC */ \
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
-	MUX_VAL(CP(GPMC_A2),		(IEN  | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
+	MUX_VAL(CP(GPMC_A2),		(IEN  | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
 	MUX_VAL(CP(GPMC_A5),		(IEN  | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\
 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\
-	MUX_VAL(CP(GPMC_A7),		(IEN  | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
+	MUX_VAL(CP(GPMC_A7),		(IEN  | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
 	MUX_VAL(CP(GPMC_A8),		(IEN  | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\
 	MUX_VAL(CP(GPMC_A9),		(IEN  | PTD | EN  | M4)) /* GPIO_42: MOTION_INT_N */\
 	MUX_VAL(CP(GPMC_A10),		(IEN  | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\
@@ -129,7 +129,7 @@
 	MUX_VAL(CP(CAM_VS),		(IEN  | PTD | EN  | M0)) /* CAM_VS */ \
 	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \
 	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTD | EN  | M0)) /* CAM_PCLK */ \
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
 	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M2)) /* CSI2_DX2 */ \
 	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M2)) /* CSI2_DY2 */ \
 	MUX_VAL(CP(CAM_D2),		(IDIS | PTD | EN  | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \
@@ -156,12 +156,12 @@
 	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /* MCBSP2_DR */ \
 	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \
 	/* MMC1 */ \
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) /* MMC1_CMD */ \
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) /* MMC1_DAT0 */ \
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) /* MMC1_DAT1 */ \
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) /* MMC1_DAT2 */ \
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) /* MMC1_DAT3 */ \
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTD | DIS | M0)) /* MMC1_CLK */ \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTD | DIS | M0)) /* MMC1_CMD */ \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTD | DIS | M0)) /* MMC1_DAT0 */ \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTD | DIS | M0)) /* MMC1_DAT1 */ \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTD | DIS | M0)) /* MMC1_DAT2 */ \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTD | DIS | M0)) /* MMC1_DAT3 */ \
 	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | DIS | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTD | DIS | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTD | DIS | M7)) /* SAFE_MODE */ \
@@ -183,15 +183,15 @@
 	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /* MCBSP3_CLKX */ \
 	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /* MCBSP3_FSX */ \
 	/* UART2 */ \
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | DIS | M0)) /* UART2_CTS */ \
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTU | DIS | M0)) /* UART2_RTS */ \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M0)) /* UART2_CTS */ \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /* UART2_RTS */ \
 	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /* UART2_TX */ \
 	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) /* UART2_RX */ \
 	/* UART1 */ \
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTU | DIS | M0)) /* UART1_TX */ \
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTU | DIS | M0)) /* UART1_RTS */ \
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) /* UART1_CTS */ \
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTU | DIS | M0)) /* UART1_RX */ \
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /* UART1_TX */ \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /* UART1_RTS */ \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTD | DIS | M0)) /* UART1_CTS */ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /* UART1_RX */ \
 	/* MCBSP4 */ \
 	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \
 	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \
@@ -227,11 +227,11 @@
 	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /* I2C1_SCL */ \
 	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /* I2C1_SDA */ \
 	/* I2C2 */ \
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | DIS | M0)) /* I2C2_SCL */ \
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | DIS | M0)) /* I2C2_SDA */ \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTD | DIS | M0)) /* I2C2_SCL */ \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTD | DIS | M0)) /* I2C2_SDA */ \
 	/* I2C3 */ \
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | DIS | M0)) /* I2C3_SCL */ \
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | DIS | M0)) /* I2C3_SDA */ \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTD | DIS | M0)) /* I2C3_SCL */ \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTD | DIS | M0)) /* I2C3_SDA */ \
 	/* I2C4 */ \
 	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /* I2C4_SCL */ \
 	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /* I2C4_SDA */ \
@@ -242,13 +242,13 @@
 	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | EN  | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M7)) /* SAFE_MODE */ \
-	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT  */ \
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
-	MUX_VAL(CP(MCSPI1_CS3),		(IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT  */ \
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
+	MUX_VAL(CP(MCSPI1_CS3),		(IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
 	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M0)) /* MCSPI2_CLK */ \
 	MUX_VAL(CP(MCSPI2_SIMO),	(IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \
 	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /* MCSPI2_SOMI */ \
-	MUX_VAL(CP(MCSPI2_CS0),		(IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
+	MUX_VAL(CP(MCSPI2_CS0),		(IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
 	MUX_VAL(CP(MCSPI2_CS1),		(IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \
 	/* SYS */ \
 	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /* SYS_32K */ \
@@ -262,25 +262,25 @@
 	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | EN  | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTU | EN  | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(SYS_OFF_MODE),	(IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTD | EN  | M7)) /* SAFE_MODE */ \
 	/* JTAG */ \
 	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /* JTAG_NTRST */ \
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /* JTAG_TCK */ \
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTU | EN  | M0)) /* JTAG_TMS */ \
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTU | EN  | M0)) /* JTAG_TDI */ \
-	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTU | DIS | M0)) /* JTAG_EMU0 */ \
-	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTU | DIS | M0)) /* JTAG_EMU1 */ \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /* JTAG_EMU0 */ \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /* JTAG_EMU1 */ \
 	/* ETK */ \
 	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTD | DIS | M2)) /* SDMMC3_CLK */ \
 	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /* SDMMC3_CMD */ \
 	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | EN  | M4)) /* GPIO_14: PROX_OUT */ \
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
 	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \
 	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | EN  | M4)) /* GPIO_21: IPC_SRDY */ \
 	MUX_VAL(CP(ETK_D8_ES2),		(IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \
 	MUX_VAL(CP(ETK_D9_ES2),		(IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \
@@ -330,7 +330,7 @@
 	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /* D2D_MCAD36 */ \
 	MUX_VAL(CP(D2D_CLK26MI),	(IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \
 	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTU | EN  | M0)) /* D2D_NRESPWRON */ \
-	MUX_VAL(CP(D2D_NRESWARM),	(IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \
+	MUX_VAL(CP(D2D_NRESWARM),	(IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \
 	MUX_VAL(CP(D2D_ARM9NIRQ),	(IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \
 	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \
 	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | DIS | M0)) /* D2D_SPINT */ \
@@ -355,8 +355,8 @@
 	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /* D2D_SREAD */ \
 	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \
 	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \
 	MUX_VAL(CP(GPIO127),		(IEN  | PTD | DIS | M7)) /* SAFE_MODE */ \
 	MUX_VAL(CP(GPIO126),		(IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \
 	MUX_VAL(CP(GPIO128),		(IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \