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| author | Po Liu <po.liu@freescale.com> | 2013-11-26 14:34:07 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-12-04 14:54:32 -0800 |
| commit | 380b8f307c5291016e1249ccd263876f0e9c1278 (patch) | |
| tree | 78be365c63e24410f42edaebc30a5ec4895b9fc5 /board | |
| parent | c3cc02af6ce6f4ff2fa494aeb4dbf1e037254877 (diff) | |
| download | talos-obmc-uboot-380b8f307c5291016e1249ccd263876f0e9c1278.tar.gz talos-obmc-uboot-380b8f307c5291016e1249ccd263876f0e9c1278.zip | |
powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
Currently, there is only one EEPROM on c29xpcie board which is AT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/c29xpcie/ddr.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 968655c1b3..7c915b036f 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/fsl_law.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> @@ -92,3 +93,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; } } + +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} |
