diff options
| author | Tom Rini <trini@ti.com> | 2013-03-21 04:30:02 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-24 12:49:12 -0400 |
| commit | c7ba18ad4b52d35b0166eeecbe05a0e1560e00ec (patch) | |
| tree | 41bf75e39b2d1b2e4e0edfdd9843f1d8495d7994 /board/ti | |
| parent | ea7b96b6aa06fea40547333e8796f8ea9a856d67 (diff) | |
| download | talos-obmc-uboot-c7ba18ad4b52d35b0166eeecbe05a0e1560e00ec.tar.gz talos-obmc-uboot-c7ba18ad4b52d35b0166eeecbe05a0e1560e00ec.zip | |
am335x_evm: Add better timings for the new BeagleBoard DDR3 part
Tested-by: Rao Bodapati <rao@circuitco.com>
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/ti')
| -rw-r--r-- | board/ti/am335x/board.c | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index d61d650ea3..12620bb69c 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -208,6 +208,14 @@ static const struct ddr_data ddr3_data = { .datadldiff0 = PHY_DLL_LOCK_DIFF, }; +static const struct ddr_data ddr3_beagleblack_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + static const struct ddr_data ddr3_evm_data = { .datardsratio0 = MT41J512M8RH125_RD_DQS, .datawdsratio0 = MT41J512M8RH125_WR_DQS, @@ -230,6 +238,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; +static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd0csratio = MT41J512M8RH125_RATIO, .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, @@ -255,6 +277,16 @@ static struct emif_regs ddr3_emif_reg_data = { PHY_EN_DYN_PWRDN, }; +static struct emif_regs ddr3_beagleblack_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + static struct emif_regs ddr3_evm_emif_reg_data = { .sdram_config = MT41J512M8RH125_EMIF_SDCFG, .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, @@ -343,9 +375,14 @@ void s_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - if (board_is_evm_sk() || board_is_bone_lt()) + if (board_is_evm_sk()) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + else if (board_is_bone_lt()) + config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE, + &ddr3_beagleblack_data, + &ddr3_beagleblack_cmd_ctrl_data, + &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later()) config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); |
