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| author | Vitaly Andrianov <vitalya@ti.com> | 2015-09-19 16:26:40 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-10-22 14:22:15 -0400 |
| commit | bda920c65e7cc299e6ef0dc6e676fe672609ce12 (patch) | |
| tree | 62ea0859242e5188851daaf365c843eefb495157 /board/ti | |
| parent | f9c4a51c3e1bc73c5c2ae178cf41aa85bada1fc8 (diff) | |
| download | talos-obmc-uboot-bda920c65e7cc299e6ef0dc6e676fe672609ce12.tar.gz talos-obmc-uboot-bda920c65e7cc299e6ef0dc6e676fe672609ce12.zip | |
ARM: k2g: Add pll data
Add pll data for k2g
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti')
| -rw-r--r-- | board/ti/ks2_evm/Makefile | 1 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board_k2g.c | 63 |
2 files changed, 64 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 071dbee180..b7c5402226 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o +obj-$(CONFIG_K2G_EVM) += board_k2g.o diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c new file mode 100644 index 0000000000..6234baa793 --- /dev/null +++ b/board/ti/ks2_evm/board_k2g.c @@ -0,0 +1,63 @@ +/* + * K2G EVM : Board initialization + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/clock.h> + +static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; +static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; +static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; +static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; +static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10}; + +struct pll_init_data *get_pll_init_data(int pll) +{ + struct pll_init_data *data = NULL; + + switch (pll) { + case MAIN_PLL: + data = &main_pll_config; + break; + case TETRIS_PLL: + data = &tetris_pll_config[speed]; + break; + case NSS_PLL: + data = &nss_pll_config; + break; + case UART_PLL: + data = &uart_pll_config; + break; + case DDR3_PLL: + data = &ddr_pll_config; + break; + default: + data = NULL; + } + + return data; +} + +s16 divn_val[16] = { + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + init_plls(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_init_keystone_plls(void) +{ + init_plls(); +} +#endif |
