diff options
| author | Vitaly Andrianov <vitalya@ti.com> | 2014-07-25 22:23:19 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-25 10:48:12 -0400 |
| commit | 61f66fd5a81b97478e9d14326c1059baa6626680 (patch) | |
| tree | 9739805fd9589de9edc6fb253d333b785f6d3421 /board/ti/ks2_evm/board_k2e.c | |
| parent | 9352697aa060e9b1b5d891e4490fdfa6f5ba6114 (diff) | |
| download | talos-obmc-uboot-61f66fd5a81b97478e9d14326c1059baa6626680.tar.gz talos-obmc-uboot-61f66fd5a81b97478e9d14326c1059baa6626680.zip | |
keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'board/ti/ks2_evm/board_k2e.c')
| -rw-r--r-- | board/ti/ks2_evm/board_k2e.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index d2499b7244..5472a43c43 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -25,15 +25,30 @@ unsigned int external_clk[ext_clk_count] = { [usb_clk] = 100000000, }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1200, - PASS_PLL_1000, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_800, + CORE_PLL_850, + CORE_PLL_1000, + CORE_PLL_1250, + CORE_PLL_1350, + CORE_PLL_1400, + CORE_PLL_1500, }; + +static struct pll_init_data pa_pll_config = + PASS_PLL_1000; + #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + return 0; } #endif |
