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| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2015-02-01 00:27:05 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-02-02 14:04:15 +0100 |
| commit | d133647af4d4fdaaf2dfb6a9e757c7aebd00a29e (patch) | |
| tree | 34cd14a0422fd91a3068edaf24bfceba3300618d /board/sunxi/dram_sun5i_auto.c | |
| parent | fb75d972eaf5c887ada28e73d3e84d52931d4cb0 (diff) | |
| download | talos-obmc-uboot-d133647af4d4fdaaf2dfb6a9e757c7aebd00a29e.tar.gz talos-obmc-uboot-d133647af4d4fdaaf2dfb6a9e757c7aebd00a29e.zip | |
sunxi: dram: Optionally use standard JEDEC timings for sun[457]i
In addition to the current Android magic settings, allow to optionally use
DDR3 timing parameters, which are tailored for different clock frequencies
and JEDEC speed bins. This should improve reliability and performance.
Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig
allows to use timings, which are calculated for the DDR3-1066F speed bin.
A lot of DDR3 chips, which are used in real Allwinner based devices,
support DDR3-1066F speed bin timings.
And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work
with any DDR3 chips, because this targets the slowest JEDEC speed bins.
The vendor magic values are still used by default for DRAM, but board
maintainers now have more flexibility in DRAM timings selection.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'board/sunxi/dram_sun5i_auto.c')
| -rw-r--r-- | board/sunxi/dram_sun5i_auto.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index e86b08e67b..bd9fd4bd27 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -10,18 +10,22 @@ static struct dram_para dram_para = { .density = 0, .io_width = 0, .bus_width = 0, - .cas = 9, .zq = CONFIG_DRAM_ZQ, .odt_en = 0, .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 9, .tpr0 = 0x42d899b7, .tpr1 = 0xa090, .tpr2 = 0x22a00, + .emr2 = 0x10, +#else +# include "dram_timings_sun4i.h" +#endif .tpr3 = 0, .tpr4 = 0, .tpr5 = 0, .emr1 = CONFIG_DRAM_EMR1, - .emr2 = 0x10, .emr3 = 0, }; |
