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| author | Vikas Manocha <vikas.manocha@st.com> | 2014-11-18 10:42:23 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-09 15:16:19 -0500 |
| commit | 2ce4eaf4c89e371aeb69392b68dbb2f705c28144 (patch) | |
| tree | 56c27ac25726f80f1bf7844222f8fadea3cdec8a /board/st | |
| parent | 9fa32b12370236a39090d4e42b013910d123db61 (diff) | |
| download | talos-obmc-uboot-2ce4eaf4c89e371aeb69392b68dbb2f705c28144.tar.gz talos-obmc-uboot-2ce4eaf4c89e371aeb69392b68dbb2f705c28144.zip | |
stv0991: enable ethernet support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'board/st')
| -rw-r--r-- | board/st/stv0991/stv0991.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c index bdeb53c1a7..989fb5e558 100644 --- a/board/st/stv0991/stv0991.c +++ b/board/st/stv0991/stv0991.c @@ -9,9 +9,16 @@ #include <miiphy.h> #include <asm/arch/stv0991_periph.h> #include <asm/arch/stv0991_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> +#include <netdev.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; +struct gpio_regs *const gpioa_regs = + (struct gpio_regs *) GPIOA_BASE_ADDR; + #ifdef CONFIG_SHOW_BOOT_PROGRESS void show_boot_progress(int progress) { @@ -19,11 +26,26 @@ void show_boot_progress(int progress) } #endif +void enable_eth_phy(void) +{ + /* Set GPIOA_06 pad HIGH (Appli board)*/ + writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir); + writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data); +} +int board_eth_enable(void) +{ + stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4); + clock_setup(ETH_CLOCK_CFG); + enable_eth_phy(); + return 0; +} + /* * Miscellaneous platform dependent initialisations */ int board_init(void) { + board_eth_enable(); return 0; } @@ -33,6 +55,7 @@ int board_uart_init(void) clock_setup(UART_CLOCK_CFG); return 0; } + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { @@ -52,3 +75,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0) + ret++; +#endif + return ret; +} +#endif |
