ppc4xx: Big cleanup of PPC4xx defines

This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>

2 files changed, 113 insertions, 113 deletions

diff --git a/board/sc3/init.S b/board/sc3/init.S
index f97a5ea610..6052c66553 100644
--- a/board/sc3/init.S
+++ b/board/sc3/init.S
@@ -58,7 +58,7 @@ ext_bus_cntlr_init:
  * We need the current boot up configuration to set correct
  * timings into internal flash and external flash
  */
-		mfdcr r24,strap			/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
+		mfdcr r24,CPC0_PSR		/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
 						   0 0 -> 8 bit external ROM
 						   0 1 -> 16 bit internal ROM */
 		addi r4,0,2
@@ -113,8 +113,8 @@ ext_bus_cntlr_init:
  * We only have to change the timing. Mapping is ok by boot-strapping
  *----------------------------------------------------------------------- */
 
-		li r4,pb0ap				/* PB0AP=Peripheral Bank 0 Access Parameters */
-		mtdcr ebccfga,r4
+		li r4,PB1AP				/* PB0AP=Peripheral Bank 0 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
 
 		mr r4,r26				/* assume internal fast flash is boot flash */
 		cmpwi r24,0x2000			/* assumption true? ... */
@@ -122,27 +122,27 @@ ext_bus_cntlr_init:
 		mr r4,r25				/* ...no, use the slow variant */
 		mr r25,r26				/* use this for the other flash */
 1:
-		mtdcr ebccfgd,r4			/* change timing now */
+		mtdcr EBC0_CFGDATA,r4			/* change timing now */
 
-		li r4,pb0cr				/* PB0CR=Peripheral Bank 0 Control Register */
-		mtdcr ebccfga,r4
-		mfdcr r4,ebccfgd
+		li r4,PB0CR				/* PB0CR=Peripheral Bank 0 Control Register */
+		mtdcr EBC0_CFGADDR,r4
+		mfdcr r4,EBC0_CFGDATA
 		lis r3,0x0001
 		ori r3,r3,0x8000			/* allow reads and writes */
 		or r4,r4,r3
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
 /*-----------------------------------------------------------------------
  * Memory Bank 3 (Second-Flash) initialization
  * 0xF0000000...0xF01FFFFF -> 2MB
  *----------------------------------------------------------------------- */
 
-		li r4,pb3ap				/* Peripheral Bank 1 Access Parameter */
-		mtdcr ebccfga,r4
-		mtdcr ebccfgd,r2			/* change timing */
+		li r4,PB3AP				/* Peripheral Bank 1 Access Parameter */
+		mtdcr EBC0_CFGADDR,r4
+		mtdcr EBC0_CFGDATA,r2			/* change timing */
 
-		li r4,pb3cr				/* Peripheral Bank 1 Configuration Registers */
-		mtdcr ebccfga,r4
+		li r4,PB3CR				/* Peripheral Bank 1 Configuration Registers */
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0xF003
 		ori r4,r4,0x8000
@@ -151,7 +151,7 @@ ext_bus_cntlr_init:
  */
 		xori r24,r24,0x2000			/* invert current bus width */
 		or r4,r4,r24
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
 /*-----------------------------------------------------------------------
  * Memory Bank 1 (NAND-Flash) initialization
@@ -169,28 +169,28 @@ ext_bus_cntlr_init:
  * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
  *----------------------------------------------------------------------- */
 
-		li r4,pb1ap				/* Peripheral Bank 1 Access Parameter */
-		mtdcr ebccfga,r4
+		li r4,PB1AP				/* Peripheral Bank 1 Access Parameter */
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0x0000
 		ori r4,r4,0x0200
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
-		li r4,pb1cr				/* Peripheral Bank 1 Configuration Registers */
-		mtdcr ebccfga,r4
+		li r4,PB1CR				/* Peripheral Bank 1 Configuration Registers */
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0x77D1
 		ori r4,r4,0x8000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
 
 /* USB init (without acceleration) */
 #ifndef CONFIG_ISP1161_PRESENT
-		li r4,pb4ap				/* PB4AP=Peripheral Bank 4 Access Parameters */
-		mtdcr ebccfga,r4
+		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
 		lis r4,0x0180
 		ori r4,r4,0x5940
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 #endif
 
 /*-----------------------------------------------------------------------
@@ -204,8 +204,8 @@ ext_bus_cntlr_init:
  A7/A24=0 -> memory cycle
  A7/ /A24=1 -> I/O cycle
 */
-		li r4,pb2ap				/* PB2AP=Peripheral Bank 2 Access Parameters */
-		mtdcr ebccfga,r4
+		li r4,PB2AP				/* PB2AP=Peripheral Bank 2 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
 /*
  We emulate an ISA access
 
@@ -226,58 +226,58 @@ ext_bus_cntlr_init:
 		lis r4,0x0100
 		ori r4,r4,0x0340
 #endif
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
 #ifdef IDE_USES_ISA_EMULATION
-		li r25,pb5ap				/* PB5AP=Peripheral Bank 5 Access Parameters */
-		mtdcr ebccfga,r25
-		mtdcr ebccfgd,r4
+		li r25,PB5AP				/* PB5AP=Peripheral Bank 5 Access Parameters */
+		mtdcr EBC0_CFGADDR,r25
+		mtdcr EBC0_CFGDATA,r4
 #endif
 
-		li r25,pb6ap				/* PB6AP=Peripheral Bank 6 Access Parameters */
-		mtdcr ebccfga,r25
-		mtdcr ebccfgd,r4
-		li r25,pb7ap				/* PB7AP=Peripheral Bank 7 Access Parameters */
-		mtdcr ebccfga,r25
-		mtdcr ebccfgd,r4
+		li r25,PB6AP				/* PB6AP=Peripheral Bank 6 Access Parameters */
+		mtdcr EBC0_CFGADDR,r25
+		mtdcr EBC0_CFGDATA,r4
+		li r25,PB7AP				/* PB7AP=Peripheral Bank 7 Access Parameters */
+		mtdcr EBC0_CFGADDR,r25
+		mtdcr EBC0_CFGDATA,r4
 
-		li r25,pb2cr				/* PB2CR=Peripheral Bank 2 Configuration Register */
-		mtdcr ebccfga,r25
+		li r25,PB2CR				/* PB2CR=Peripheral Bank 2 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
 
 		lis r4,0x780B
 		ori r4,r4,0xA000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 /*
  * the other areas are only 1MiB in size
  */
 		lis r4,0x7401
 		ori r4,r4,0xA000
 
-		li r25,pb6cr				/* PB6CR=Peripheral Bank 6 Configuration Register */
-		mtdcr ebccfga,r25
+		li r25,PB6CR				/* PB6CR=Peripheral Bank 6 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
 		lis r4,0x7401
 		ori r4,r4,0xA000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
-		li r25,pb7cr				/* PB7CR=Peripheral Bank 7 Configuration Register */
-		mtdcr ebccfga,r25
+		li r25,PB7CR				/* PB7CR=Peripheral Bank 7 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
 		lis r4,0x7411
 		ori r4,r4,0xA000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
 #ifndef CONFIG_ISP1161_PRESENT
-		li r25,pb4cr				/* PB4CR=Peripheral Bank 4 Configuration Register */
-		mtdcr ebccfga,r25
+		li r25,PB4CR				/* PB4CR=Peripheral Bank 4 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
 		lis r4,0x7421
 		ori r4,r4,0xA000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 #endif
 #ifdef IDE_USES_ISA_EMULATION
-		li r25,pb5cr				/* PB5CR=Peripheral Bank 5 Configuration Register */
-		mtdcr ebccfga,r25
+		li r25,PB5CR				/* PB5CR=Peripheral Bank 5 Configuration Register */
+		mtdcr EBC0_CFGADDR,r25
 		lis r4,0x0000
 		ori r4,r4,0x0000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 #endif
 
 /*-----------------------------------------------------------------------
@@ -315,19 +315,19 @@ ext_bus_cntlr_init:
 
 #ifdef CONFIG_ISP1161_PRESENT
 
-		li r4,pb4ap				/* PB4AP=Peripheral Bank 4 Access Parameters */
-		mtdcr ebccfga,r4
+		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0x030D
 		ori r4,r4,0x5E80
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
-		li r4,pb4cr				/* PB2CR=Peripheral Bank 4 Configuration Register */
-		mtdcr ebccfga,r4
+		li r4,PB4CR				/* PB2CR=Peripheral Bank 4 Configuration Register */
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0x77C1
 		ori r4,r4,0xA000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
 #endif
 
@@ -352,28 +352,28 @@ ext_bus_cntlr_init:
  *
  *----------------------------------------------------------------------- */
 
-		li r4,pb5ap
-		mtdcr ebccfga,r4
+		li r4,PB5AP
+		mtdcr EBC0_CFGADDR,r4
 		lis r4,0x040C
 		ori r4,r4,0x0200
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 
-		li r4,pb5cr			/* PB2CR=Peripheral Bank 2 Configuration Register */
-		mtdcr ebccfga,r4
+		li r4,PB5CR			/* PB2CR=Peripheral Bank 2 Configuration Register */
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0x7A01
 		ori r4,r4,0xA000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 #endif
 /*
  * External Peripheral Control Register
  */
-		li r4,epcr
-		mtdcr ebccfga,r4
+		li r4,EBC0_CFG
+		mtdcr EBC0_CFGADDR,r4
 
 		lis r4,0xB84E
 		ori r4,r4,0xF000
-		mtdcr ebccfgd,r4
+		mtdcr EBC0_CFGDATA,r4
 /*
  * drive POST code
  */
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index 6c82fe7e99..5ae7b1244a 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -199,14 +199,14 @@ int board_start_ide(void)
 static int sc3_cameron_init (void)
 {
 	/* Set up the Memory Controller for the CAMERON version */
-	mtebc (pb4ap, 0x01805940);
-	mtebc (pb4cr, 0x7401a000);
-	mtebc (pb5ap, 0x01805940);
-	mtebc (pb5cr, 0x7401a000);
-	mtebc (pb6ap, 0x0);
-	mtebc (pb6cr, 0x0);
-	mtebc (pb7ap, 0x0);
-	mtebc (pb7cr, 0x0);
+	mtebc (PB4AP, 0x01805940);
+	mtebc (PB4CR, 0x7401a000);
+	mtebc (PB5AP, 0x01805940);
+	mtebc (PB5CR, 0x7401a000);
+	mtebc (PB6AP, 0x0);
+	mtebc (PB6CR, 0x0);
+	mtebc (PB7AP, 0x0);
+	mtebc (PB7CR, 0x0);
 	return 0;
 }
 
@@ -312,18 +312,18 @@ int board_early_init_f (void)
 	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
 
 	/* setup other implementation specific details */
-	mtdcr (ecr, 0x60606000);
+	mtdcr (CPC0_ECR, 0x60606000);
 
-	mtdcr (cntrl1, 0x000042C0);
+	mtdcr (CPC0_CR1, 0x000042C0);
 
 	if (IS_CAMERON) {
-		mtdcr (cntrl0, 0x01380000);
+		mtdcr (CPC0_CR0, 0x01380000);
 		/* Setup the GPIOs */
 		writel (0x08008000, 0xEF600700);	/* Output states */
 		writel (0x00000000, 0xEF600718);	/* Open Drain control */
 		writel (0x68098000, 0xEF600704);	/* Output control */
 	} else {
-		mtdcr (cntrl0,0x00080000);
+		mtdcr (CPC0_CR0,0x00080000);
 		/* Setup the GPIOs */
 		writel (0x08000000, 0xEF600700);	/* Output states */
 		writel (0x14000000, 0xEF600718);	/* Open Drain control */
@@ -331,13 +331,13 @@ int board_early_init_f (void)
 	}
 
 	/* Code decompression disabled */
-	mtdcr (kiar, kconf);
-	mtdcr (kidr, 0x2B);
+	mtdcr (KIAR, KCONF);
+	mtdcr (KIDR, 0x2B);
 
 	/* CPC0_ER: enable sleep mode of (currently) unused components */
 	/* CPC0_FR: force unused components into sleep mode */
-	mtdcr (cpmer, 0x3F800000);
-	mtdcr (cpmfr, 0x14000000);
+	mtdcr (CPMER, 0x3F800000);
+	mtdcr (CPMFR, 0x14000000);
 
 	/* set PLB priority */
 	mtdcr (0x87, 0x08000000);
@@ -472,19 +472,19 @@ static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
 
 #ifdef SC3_DEBUGOUT
 
-static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
-				pb5ap, pb6ap, pb7ap};
-static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
-				pb5cr, pb6cr, pb7cr};
+static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
+				PB5AP, PB6AP, PB7AP};
+static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
+				PB5CR, PB6CR, PB7CR};
 
 static int show_reg (int nr)
 {
 	unsigned long ul1, ul2;
 
-	mtdcr (ebccfga, ap[nr]);
-	ul1 = mfdcr (ebccfgd);
-	mtdcr (ebccfga, cr[nr]);
-	ul2 = mfdcr(ebccfgd);
+	mtdcr (EBC0_CFGADDR, ap[nr]);
+	ul1 = mfdcr (EBC0_CFGDATA);
+	mtdcr (EBC0_CFGADDR, cr[nr]);
+	ul2 = mfdcr(EBC0_CFGDATA);
 	printCSConfig(nr, ul1, ul2);
 	return 0;
 }
@@ -500,8 +500,8 @@ int checkboard (void)
 		show_reg (i);
 	}
 
-	mtdcr (ebccfga, epcr);
-	ul1 = mfdcr (ebccfgd);
+	mtdcr (EBC0_CFGADDR, EBC0_CFG);
+	ul1 = mfdcr (EBC0_CFGDATA);
 
 	puts ("\nGeneral configuration:\n");
 
@@ -591,21 +591,21 @@ phys_size_t initdram (int board_type)
 
 	puts("\nSDRAM configuration:\n");
 
-	mtdcr (memcfga, mem_mcopt1);
-	ul1 = mfdcr(memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
 
 	if (!(ul1 & 0x80000000)) {
 		puts(" Controller disabled\n");
 		return 0;
 	}
 	for (i = 0; i < 4; i++) {
-		mtdcr (memcfga, mbcf[i]);
-		ul1 = mfdcr (memcfgd);
+		mtdcr (SDRAM0_CFGADDR, mbcf[i]);
+		ul1 = mfdcr (SDRAM0_CFGDATA);
 		mems += printSDRAMConfig (i, ul1);
 	}
 
-	mtdcr (memcfga, mem_sdtr1);
-	ul1 = mfdcr(memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
 
 	printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
 	printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
@@ -614,15 +614,15 @@ phys_size_t initdram (int board_type)
 	printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
 	printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
 	puts ("Misc:\n");
-	mtdcr (memcfga, mem_rtr);
-	ul1 = mfdcr(memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
 	printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
 
-	mtdcr(memcfga,mem_pmit);
-	ul2=mfdcr(memcfgd);
+	mtdcr(SDRAM0_CFGADDR,mem_pmit);
+	ul2=mfdcr(SDRAM0_CFGDATA);
 
-	mtdcr(memcfga,mem_mcopt1);
-	ul1=mfdcr(memcfgd);
+	mtdcr(SDRAM0_CFGADDR,mem_mcopt1);
+	ul1=mfdcr(SDRAM0_CFGDATA);
 
 	if (ul1 & 0x20000000)
 		printf(" -Power Down after: %luns\n",
@@ -658,8 +658,8 @@ phys_size_t initdram (int board_type)
 	else
 		puts(" -Memory lines only at write cycles active outputs\n");
 
-	mtdcr (memcfga, mem_status);
-	ul1 = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_status);
+	ul1 = mfdcr (SDRAM0_CFGDATA);
 	if (ul1 & 0x80000000)
 		puts(" -SDRAM Controller ready\n");
 	else
@@ -670,20 +670,20 @@ phys_size_t initdram (int board_type)
 
 	return (mems * 1024 * 1024);
 #else
-	mtdcr (memcfga, mem_mb0cf);
-	ul1 = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	ul1 = mfdcr (SDRAM0_CFGDATA);
 	mems = printSDRAMConfig (0, ul1);
 
-	mtdcr (memcfga, mem_mb1cf);
-	ul1 = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	ul1 = mfdcr (SDRAM0_CFGDATA);
 	mems += printSDRAMConfig (1, ul1);
 
-	mtdcr (memcfga, mem_mb2cf);
-	ul1 = mfdcr(memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
 	mems += printSDRAMConfig (2, ul1);
 
-	mtdcr (memcfga, mem_mb3cf);
-	ul1 = mfdcr(memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+	ul1 = mfdcr(SDRAM0_CFGDATA);
 	mems += printSDRAMConfig (3, ul1);
 
 	return (mems * 1024 * 1024);