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| author | Scott Ellis <scott@jumpnowtek.com> | 2010-01-27 11:11:46 -0500 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2010-02-12 12:31:53 -0600 |
| commit | 093d6018cf0a8dae614c2924c0013d97e2a48662 (patch) | |
| tree | 6a90d9044f86253d8e638d706716dc2e7855cf30 /board/overo/overo.c | |
| parent | 63a47dfd07536e399665ca7504bac512bf21491e (diff) | |
| download | talos-obmc-uboot-093d6018cf0a8dae614c2924c0013d97e2a48662.tar.gz talos-obmc-uboot-093d6018cf0a8dae614c2924c0013d97e2a48662.zip | |
Overo GPMC registers
Use appropriate GPMC timings for the LAN9221 controller on the
Gumstix Overo expansion boards not the values in arch-omap3/mem.h
which are for a different ethernet controller.
Signed-off-by: Scott Ellis <scott@jumpnowtek.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'board/overo/overo.c')
| -rw-r--r-- | board/overo/overo.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/overo/overo.c b/board/overo/overo.c index f363281568..e85be7d5e6 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -100,13 +100,13 @@ static void setup_net_chip(void) struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); - writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); - writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); - writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); - writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); - writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); - writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
