Code cleanup; make several boards compile & link.

3 files changed, 248 insertions, 226 deletions

diff --git a/board/integratorap/config.mk b/board/integratorap/config.mk
index df674917a5..25b79b3e79 100644
--- a/board/integratorap/config.mk
+++ b/board/integratorap/config.mk
@@ -1,5 +1,5 @@
 #
-# image should be loaded at 0x01000000 
+# image should be loaded at 0x01000000
 #
 
 TEXT_BASE = 0x01000000
diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
index 960ec3a265..84a4c70782 100644
--- a/board/integratorap/integratorap.c
+++ b/board/integratorap/integratorap.c
@@ -105,146 +105,161 @@ static struct pci_config_table pci_integrator_config_table[] = {
 };
 #endif
 
-// V3 access routines
+/* V3 access routines */
 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
 #define _V3Read16(o)    (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
 
 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
 #define _V3Read32(o)    (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
 
-// Compute address necessary to access PCI config space for the given
-// bus and device.
-#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
-    ({                                                                   		\
-    unsigned int __address, __devicebit;							\
-    unsigned short __mapaddress;								\
-    unsigned int __dev = PCI_DEV(__devfn);	/* FIXME to check!! (slot?) */	\
+/* Compute address necessary to access PCI config space for the given */
+/* bus and device. */
+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({				\
+	unsigned int __address, __devicebit;						\
+	unsigned short __mapaddress;							\
+	unsigned int __dev = PCI_DEV (__devfn);	/* FIXME to check!! (slot?) */		\
 											\
-    if (__bus == 0) {									\
-	/* local bus segment so need a type 0 config cycle */				\
-        /* build the PCI configuration "address" with one-hot in A31-A11 */		\
-        __address = PCI_CONFIG_BASE;							\
-        __address |= ((__devfn & 0x07) << 8);						\
-        __address |= __offset & 0xFF;							\
-        __mapaddress = 0x000A;    /* 101=>config cycle, 0=>A1=A0=0 */			\
-        __devicebit = (1 << (__dev + 11));						\
+	if (__bus == 0) {								\
+		/* local bus segment so need a type 0 config cycle */			\
+		/* build the PCI configuration "address" with one-hot in A31-A11 */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__devfn & 0x07) << 8);					\
+		__address |= __offset & 0xFF;						\
+		__mapaddress = 0x000A;	/* 101=>config cycle, 0=>A1=A0=0 */		\
+		__devicebit = (1 << (__dev + 11));					\
 											\
-        if ((__devicebit & 0xFF000000) != 0) {						\
-            /* high order bits are handled by the MAP register */			\
-            __mapaddress |= (__devicebit >> 16);					\
-        } else {									\
-            /* low order bits handled directly in the address */			\
-            __address |= __devicebit;							\
-        }										\
-    } else {	/* bus !=0 */								\
-        /* not the local bus segment so need a type 1 config cycle */			\
-        /* A31-A24 are don't care (so clear to 0) */					\
-        __mapaddress = 0x000B;    /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
-        __address = PCI_CONFIG_BASE;							\
-        __address |= ((__bus & 0xFF) << 16);  	/* bits 23..16 = bus number 	*/	\
-        __address |= ((__dev & 0x1F) << 11);  	/* bits 15..11 = device number  */	\
-        __address |= ((__devfn & 0x07) << 8);  	/* bits 10..8  = function number*/	\
-        __address |= __offset & 0xFF;  		/* bits  7..0  = register number*/	\
-    }											\
-    _V3Write16(V3_LB_MAP1, __mapaddress);						\
+		if ((__devicebit & 0xFF000000) != 0) {					\
+			/* high order bits are handled by the MAP register */		\
+			__mapaddress |= (__devicebit >> 16);				\
+		} else {								\
+			/* low order bits handled directly in the address */		\
+			__address |= __devicebit;					\
+		}									\
+	} else {		/* bus !=0 */						\
+		/* not the local bus segment so need a type 1 config cycle */		\
+		/* A31-A24 are don't care (so clear to 0) */				\
+		__mapaddress = 0x000B;	/* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__bus & 0xFF) << 16);	/* bits 23..16 = bus number     */  \
+		__address |= ((__dev & 0x1F) << 11);	/* bits 15..11 = device number  */  \
+		__address |= ((__devfn & 0x07) << 8);	/* bits 10..8  = function number */ \
+		__address |= __offset & 0xFF;	/* bits  7..0  = register number */	\
+	}										\
+	_V3Write16 (V3_LB_MAP1, __mapaddress);						\
+	__address;									\
+})
+
+/* _V3OpenConfigWindow - open V3 configuration window */
+#define _V3OpenConfigWindow() {								\
+	/* Set up base0 to see all 512Mbytes of memory space (not	     */		\
+	/* prefetchable), this frees up base1 for re-use by configuration*/		\
+	/* memory */									\
 											\
-    __address;										\
-    })
-
-// _V3OpenConfigWindow - open V3 configuration window
-#define _V3OpenConfigWindow() 							\
-    {										\
-    /* Set up base0 to see all 512Mbytes of memory space (not	     */		\
-    /* prefetchable), this frees up base1 for re-use by configuration*/		\
-    /* memory */								\
-										\
-    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
-			     0x90 | V3_LB_BASE_M_ENABLE));			\
-    /* Set up base1 to point into configuration space, note that MAP1 */	\
-    /* register is set up by pciMakeConfigAddress(). */				\
-										\
-    _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |		\
-			     0x40 | V3_LB_BASE_M_ENABLE));			\
-    }
-
-// _V3CloseConfigWindow - close V3 configuration window
-#define _V3CloseConfigWindow()							\
-    {										\
-    /* Reassign base1 for use by prefetchable PCI memory */			\
-    _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
-					| 0x84 | V3_LB_BASE_M_ENABLE));		\
-    _V3Write16 (V3_LB_MAP1,							\
-	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
-										\
-    /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
-										\
-    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
-			     0x80 | V3_LB_BASE_M_ENABLE));			\
-    }
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+				     0x90 | V3_LB_BASE_M_ENABLE));			\
+	/* Set up base1 to point into configuration space, note that MAP1 */		\
+	/* register is set up by pciMakeConfigAddress(). */				\
+											\
+	_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |			\
+				     0x40 | V3_LB_BASE_M_ENABLE));			\
+}
 
+/* _V3CloseConfigWindow - close V3 configuration window */
+#define _V3CloseConfigWindow() {							\
+    /* Reassign base1 for use by prefetchable PCI memory */				\
+	_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
+					| 0x84 | V3_LB_BASE_M_ENABLE));			\
+	_V3Write16 (V3_LB_MAP1,								\
+	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
+											\
+	/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
+											\
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+			     0x80 | V3_LB_BASE_M_ENABLE));				\
+}
 
-static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev,
-				    int offset, unsigned char *val)
+static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned char *val)
 {
-    _V3OpenConfigWindow();
-    *val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							       PCI_FUNC (dev),
+							       offset);
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev,
-				     int offset, unsigned short *val)
+static int pci_integrator_read__word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short *val)
 {
-    _V3OpenConfigWindow();
-    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev,
-				     int offset, unsigned int *val)
+static int pci_integrator_read_dword (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned int *val)
 {
-    _V3OpenConfigWindow();
-    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
-    *val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16;
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	*val |= (*(volatile unsigned int *)
+		 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
+				     (offset + 2))) << 16;
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev,
-				     int offset, unsigned char val)
+static int pci_integrator_write_byte (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned char val)
 {
-    _V3OpenConfigWindow();
-    *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							PCI_FUNC (dev),
+							offset) = val;
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev,
-				     int offset,unsigned short val)
+static int pci_integrator_write_word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short val)
 {
-    _V3OpenConfigWindow();
-    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = val;
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev,
-				      int offset, unsigned int val)
+static int pci_integrator_write_dword (struct pci_controller *hose,
+				       pci_dev_t dev, int offset,
+				       unsigned int val)
 {
-    _V3OpenConfigWindow();
-    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF);
-    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF);
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = (val & 0xFFFF);
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 (offset + 2)) = ((val >> 16) & 0xFFFF);
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
-
 /******************************
  * PCI initialisation
  ******************************/
@@ -255,176 +270,184 @@ struct pci_controller integrator_hose = {
 #endif
 };
 
-void pci_init_board(void)
+void pci_init_board (void)
 {
-    volatile int i, j;
-    struct pci_controller *hose = &integrator_hose;
+	volatile int i, j;
+	struct pci_controller *hose = &integrator_hose;
 
-    /* setting this register will take the V3 out of reset */
+	/* setting this register will take the V3 out of reset */
 
-    *(volatile unsigned int *)(INTEGRATOR_SC_PCIENABLE) = 1;
+	*(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
 
-    /* wait a few usecs to settle the device and the PCI bus */
+	/* wait a few usecs to settle the device and the PCI bus */
 
-    for (i = 0; i < 100 ; i++)
-	   j = i + 1;
+	for (i = 0; i < 100; i++)
+		j = i + 1;
 
-    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
+	/* Now write the Base I/O Address Word to V3_BASE + 0x6C */
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16);
+	*(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
+		(unsigned short) (V3_BASE >> 16);
 
-    do {
-        *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
-	*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
-    } while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
-	     *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
+	do {
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
+			0x55;
+	} while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
+		 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
+						 4) != 0x55);
 
-    /* Make sure that V3 register access is not locked, if it is, unlock it */
+	/* Make sure that V3 register access is not locked, if it is, unlock it */
 
-    if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
-				== V3_SYSTEM_M_LOCK)
-	*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = 0xA05F;
+	if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
+	     V3_SYSTEM_M_LOCK)
+	    == V3_SYSTEM_M_LOCK)
+		*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
 
-    /* Ensure that the slave accesses from PCI are disabled while we */
-    /* setup windows */
+	/* Ensure that the slave accesses from PCI are disabled while we */
+	/* setup windows */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) &=
-				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
+		~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
 
-    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
 
-    *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
+		~V3_SYSTEM_M_RST_OUT;
 
-    /* Make all accesses from PCI space retry until we're ready for them */
+	/* Make all accesses from PCI space retry until we're ready for them */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
+		V3_PCI_CFG_M_RETRY_EN;
 
-    /* Set up any V3 PCI Configuration Registers that we absolutely have to */
-    /* LB_CFG controls Local Bus protocol. */
-    /* Enable LocalBus byte strobes for READ accesses too. */
-    /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
+	/* Set up any V3 PCI Configuration Registers that we absolutely have to */
+	/* LB_CFG controls Local Bus protocol. */
+	/* Enable LocalBus byte strobes for READ accesses too. */
+	/* set bit 7 BE_IMODE and bit 6 BE_OMODE */
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
 
-    /* PCI_CMD controls overall PCI operation. */
-    /* Enable PCI bus master. */
+	/* PCI_CMD controls overall PCI operation. */
+	/* Enable PCI bus master. */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) |= 0x04;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
 
-    /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
+	/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
-					(V3_PCI_MAP_M_ADR_SIZE_512M |
-					V3_PCI_MAP_M_REG_EN |
-					V3_PCI_MAP_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
+		(INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
+					      V3_PCI_MAP_M_REG_EN |
+					      V3_PCI_MAP_M_ENABLE);
 
-    /* PCI_BASE0 is the PCI address of the start of the window */
+	/* PCI_BASE0 is the PCI address of the start of the window */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
+		INTEGRATOR_BOOT_ROM_BASE;
 
-    /* PCI_MAP1 is LOCAL address of the start of the window */
+	/* PCI_MAP1 is LOCAL address of the start of the window */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
-			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
-			 V3_PCI_MAP_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
+		(INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
+						V3_PCI_MAP_M_REG_EN |
+						V3_PCI_MAP_M_ENABLE);
 
-    /* PCI_BASE1 is the PCI address of the start of the window */
+	/* PCI_BASE1 is the PCI address of the start of the window */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
+		INTEGRATOR_HDR0_SDRAM_BASE;
 
-    /* Set up the windows from local bus memory into PCI configuration, */
-    /* I/O and Memory. */
-    /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
+	/* Set up the windows from local bus memory into PCI configuration, */
+	/* I/O and Memory. */
+	/* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
 
-    *(volatile unsigned short *)(V3_BASE +V3_LB_BASE2) =
-			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
-    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP2) = 0;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
+		((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
 
-    /* PCI Configuration, use LB_BASE1/LB_MAP1. */
+	/* PCI Configuration, use LB_BASE1/LB_MAP1. */
 
-    /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
-    /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
-    /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
+	/* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
+	/* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
+	/* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
 
-    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE0) =
-			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
+		INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP0) =
-			((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
+		((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
 
-    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+	/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
 
-    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE1) =
-			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
+		INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP1) =
-			(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
+		(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
 
-    /* Allow accesses to PCI Configuration space */
-    /* and set up A1, A0 for type 1 config cycles */
+	/* Allow accesses to PCI Configuration space */
+	/* and set up A1, A0 for type 1 config cycles */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) =
-			((*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG)) &
-			   ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
-			   V3_PCI_CFG_M_AD_LOW0;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
+		((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
+		 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
+		V3_PCI_CFG_M_AD_LOW0;
 
-    /* now we can allow in PCI MEMORY accesses */
+	/* now we can allow in PCI MEMORY accesses */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) =
-		(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
+		(*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
+		V3_COMMAND_M_MEM_EN;
 
-    /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
-    /* initialise and lock the V3 system register so that no one else */
-    /* can play with it */
+	/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
+	/* initialise and lock the V3 system register so that no one else */
+	/* can play with it */
 
-   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
-		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_RST_OUT;
 
-   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
-		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_LOCK;
 
-     /*
-      * Register the hose
-      */
-   hose->first_busno = 0;
-   hose->last_busno = 0xff;
+	/*
+	 * Register the hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
 
-   /* System memory space */
-   pci_set_region(hose->regions + 0,
-		  0x00000000, 0x40000000, 0x01000000,
-		  PCI_REGION_MEM | PCI_REGION_MEMORY);
+	/* System memory space */
+	pci_set_region (hose->regions + 0,
+			0x00000000, 0x40000000, 0x01000000,
+			PCI_REGION_MEM | PCI_REGION_MEMORY);
 
-   /* PCI Memory - config space */
-   pci_set_region(hose->regions + 1,
-		  0x00000000, 0x62000000, 0x01000000,
-		  PCI_REGION_MEM);
+	/* PCI Memory - config space */
+	pci_set_region (hose->regions + 1,
+			0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
 
-   /* PCI V3 regs */
-   pci_set_region(hose->regions + 2,
-		  0x00000000, 0x61000000, 0x00080000,
-		  PCI_REGION_MEM);
+	/* PCI V3 regs */
+	pci_set_region (hose->regions + 2,
+			0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
 
-   /* PCI I/O space */
-   pci_set_region(hose->regions + 3,
-		  0x00000000, 0x60000000, 0x00010000,
-		  PCI_REGION_IO);
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 3,
+			0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
 
-   pci_set_ops(hose,
-	       pci_integrator_read_byte,
-	       pci_integrator_read__word,
-	       pci_integrator_read_dword,
-	       pci_integrator_write_byte,
-	       pci_integrator_write_word,
-	       pci_integrator_write_dword);
+	pci_set_ops (hose,
+		     pci_integrator_read_byte,
+		     pci_integrator_read__word,
+		     pci_integrator_read_dword,
+		     pci_integrator_write_byte,
+		     pci_integrator_write_word, pci_integrator_write_dword);
 
-   hose->region_count = 4;
+	hose->region_count = 4;
 
-   pci_register_hose(hose);
+	pci_register_hose (hose);
 
-   pciauto_config_init(hose);
-   pciauto_config_device(hose, 0);
+	pciauto_config_init (hose);
+	pciauto_config_device (hose, 0);
 
-   hose->last_busno = pci_hose_scan(hose);
+	hose->last_busno = pci_hose_scan (hose);
 }
 #endif
 
@@ -452,4 +475,3 @@ int dram_init (void)
 {
 	return 0;
 }
-
diff --git a/board/integratorap/u-boot.lds b/board/integratorap/u-boot.lds
index da679c2e51..33931be127 100644
--- a/board/integratorap/u-boot.lds
+++ b/board/integratorap/u-boot.lds
@@ -43,8 +43,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-	armboot_end = .;
+	_end = .;
 }