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authorSimon Glass <sjg@chromium.org>2012-12-13 20:49:02 +0000
committerTom Rini <trini@ti.com>2013-02-04 09:05:44 -0500
commit923a662f2fb09aa67c1ec0de25474c218fad2690 (patch)
tree0619dffdc10d04edd41fbc216e6d81608fd5aac1 /board/gdsys
parent7273ccec61e26adef6149ddaf261217b30c4f8a9 (diff)
downloadtalos-obmc-uboot-923a662f2fb09aa67c1ec0de25474c218fad2690.tar.gz
talos-obmc-uboot-923a662f2fb09aa67c1ec0de25474c218fad2690.zip
ppc: Move fpga_state to arch_global_data
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/gdsys')
-rw-r--r--board/gdsys/405ep/405ep.c15
-rw-r--r--board/gdsys/405ex/405ex.c13
-rw-r--r--board/gdsys/405ex/io64.c2
3 files changed, 16 insertions, 14 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index bc9b7d0a97..6221171092 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -38,14 +38,14 @@ DECLARE_GLOBAL_DATA_PTR;
int get_fpga_state(unsigned dev)
{
- return gd->fpga_state[dev];
+ return gd->arch.fpga_state[dev];
}
void print_fpga_state(unsigned dev)
{
- if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n");
- if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n");
}
@@ -54,7 +54,7 @@ int board_early_init_f(void)
unsigned k;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] = 0;
+ gd->arch.fpga_state[k] = 0;
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
@@ -78,7 +78,7 @@ int board_early_init_r(void)
unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] = 0;
+ gd->arch.fpga_state[k] = 0;
/*
* reset FPGA
@@ -94,7 +94,8 @@ int board_early_init_r(void)
while (!gd405ep_get_fpga_done(k)) {
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
break;
}
}
@@ -126,7 +127,7 @@ int board_early_init_r(void)
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |=
+ gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
break;
}
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index 5766c0f562..32e24c08cb 100644
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -15,14 +15,14 @@ DECLARE_GLOBAL_DATA_PTR;
int get_fpga_state(unsigned dev)
{
- return gd->fpga_state[dev];
+ return gd->arch.fpga_state[dev];
}
void print_fpga_state(unsigned dev)
{
- if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n");
- if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n");
}
@@ -192,7 +192,7 @@ int board_early_init_r(void)
unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] = 0;
+ gd->arch.fpga_state[k] = 0;
/*
* reset FPGA
@@ -208,7 +208,8 @@ int board_early_init_r(void)
while (!gd405ex_get_fpga_done(k)) {
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
break;
}
}
@@ -240,7 +241,7 @@ int board_early_init_r(void)
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |=
+ gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
break;
}
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 41fdef7da8..7d2899dc94 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -359,7 +359,7 @@ void gd405ex_init(void)
if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
+ gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
} else {
pca9698_direction_output(0x22, 39, 1);
}
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