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| author | Tom Rini <trini@konsulko.com> | 2015-04-28 12:15:13 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-04-28 12:15:13 -0400 |
| commit | e536ab8849b2b4f6d68bbc8e1d1f9bc033db06bd (patch) | |
| tree | e5e3a3d5a0bee8a1d9a74deb3990455c40ded6b1 /board/freescale | |
| parent | cc555bd4f40a652471df4a3621d45ee57df0ca11 (diff) | |
| parent | 205d58699b157df75f1aa0b363ea9c21add21a0c (diff) | |
| download | talos-obmc-uboot-e536ab8849b2b4f6d68bbc8e1d1f9bc033db06bd.tar.gz talos-obmc-uboot-e536ab8849b2b4f6d68bbc8e1d1f9bc033db06bd.zip | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/common/Makefile | 3 | ||||
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 13 |
2 files changed, 6 insertions, 10 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 7181cac291..87d05780fe 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -74,8 +74,7 @@ obj-$(CONFIG_P5040DS) += p_corenet/ obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT -obj-y += fsl_validate.o -obj-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o +obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index bb2dd9624b..23f8f6b76f 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -753,10 +753,11 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = { .p1_mpwrdlctl = 0x48254A36, }; +/* MT41K128M16JT-125 */ static struct mx6_ddr3_cfg mem_ddr = { .mem_speed = 1600, - .density = 4, - .width = 64, + .density = 2, + .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, @@ -798,18 +799,14 @@ static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ - .dsize = mem_ddr.width/32, + .dsize = 2, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ .ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ -#ifdef RTT_NOM_120OHM - .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ -#else .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ -#endif .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ @@ -818,7 +815,7 @@ static void spl_dram_init(void) .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ }; - mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); } |
