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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-01 22:01:54 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-08 09:10:04 -0500 |
| commit | 2abbd31da6d900473ed678ca50789ee58bc9bb00 (patch) | |
| tree | 04faa2d9df989a87f184b745848e657dd03ff634 /board/freescale | |
| parent | 13d46ab2572c0283d34f93bebc9a41295ef84ca5 (diff) | |
| download | talos-obmc-uboot-2abbd31da6d900473ed678ca50789ee58bc9bb00.tar.gz talos-obmc-uboot-2abbd31da6d900473ed678ca50789ee58bc9bb00.zip | |
ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 9518392cdd..d1e659b46b 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -43,7 +43,6 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_PD_CONTROL 0x00000000 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 #define CONFIG_SYS_DDR_RCW_1 0x00000000 #define CONFIG_SYS_DDR_RCW_2 0x00000000 @@ -110,7 +109,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 @@ -138,7 +136,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 @@ -166,7 +163,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 @@ -194,7 +190,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL, .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
