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| author | Kumar Gala <galak@kernel.crashing.org> | 2010-07-09 09:12:18 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-07 09:49:47 -0500 |
| commit | 1bf8e9fd7498da3f9b109944b0551c589402d643 (patch) | |
| tree | 8e51b8d847f26f8358a45c05077fc8d6f9aa6250 /board/freescale | |
| parent | c2b3b6408bb011a618f67aeec1928482b679b319 (diff) | |
| download | talos-obmc-uboot-1bf8e9fd7498da3f9b109944b0551c589402d643.tar.gz talos-obmc-uboot-1bf8e9fd7498da3f9b109944b0551c589402d643.zip | |
powerpc/85xx: Add support for 4th PCI controller on corenet_ds
We configure the controller but dont have virtual address space thus any
devices on the 4th controller are not accessible in u-boot.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/corenet_ds/pci.c | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 2994e366c2..e1bca1984c 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +#ifdef CONFIG_PCIE4 +static struct pci_controller pcie4_hose; +#endif + void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; + struct fsl_pci_info pci_info[4]; u32 devdisr; int first_free_busno = 0; int num = 0; @@ -119,6 +123,28 @@ void pci_init_board(void) #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ #endif + +#ifdef CONFIG_PCIE4 + pcie_configured = is_serdes_configured(PCIE4); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { + set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_4); + set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_4); + SET_STD_PCIE_INFO(pci_info[num], 4); + pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); + printf(" PCIE4 connected to as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie4_hose, first_free_busno); + } else { + printf (" PCIE4: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ +#endif } void pci_of_setup(void *blob, bd_t *bd) |
