diff options
| author | Scott Wood <scottwood@freescale.com> | 2012-10-12 18:02:24 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2012-11-26 15:41:27 -0600 |
| commit | 13d1143ffb4dc0c71478534b6b52402e95be9420 (patch) | |
| tree | 0fb8cac0505d385547eb44f4c4afc35165ac7e62 /board/freescale/p1_p2_rdb_pc/tlb.c | |
| parent | d674bccf738396ecdc4374f5b5cb3e7fd376a0ab (diff) | |
| download | talos-obmc-uboot-13d1143ffb4dc0c71478534b6b52402e95be9420.tar.gz talos-obmc-uboot-13d1143ffb4dc0c71478534b6b52402e95be9420.zip | |
powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1_p2_rdb_pc/tlb.c')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/tlb.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 0873dd750f..3e4dffd237 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -95,6 +95,16 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1), +#else /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -106,8 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif -#endif +#endif /* P1020MBG */ +#endif /* not L2 SRAM */ +#endif /* RAMBOOT/SPL */ }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |
