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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 09:15:29 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 23:21:56 -0600 |
| commit | 4d3521cc79cabc61edf12c48c0ce318d4efb712f (patch) | |
| tree | d9f0277cf935b625961ab7ecaf8bee10c6664e8f /board/freescale/mpc8568mds/init.S | |
| parent | 572b13afc42710f2957c382a710360429c0e099b (diff) | |
| download | talos-obmc-uboot-4d3521cc79cabc61edf12c48c0ce318d4efb712f.tar.gz talos-obmc-uboot-4d3521cc79cabc61edf12c48c0ce318d4efb712f.zip | |
85xx: convert remaining 85xx boards over to use new LAW init code
Converted ATUM8548, MPC8568 MDS, MPC8540 EVAL, and TQM85xx boards over
to use new LAW init code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8568mds/init.S')
| -rw-r--r-- | board/freescale/mpc8568mds/init.S | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S index 2748c51f3b..39819ab20d 100644 --- a/board/freescale/mpc8568mds/init.S +++ b/board/freescale/mpc8568mds/init.S @@ -176,61 +176,3 @@ tlb1_entry: 2: entry_end - -/* - * LAW(Local Access Window) configuration: - * - *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB - *-) 0xe000_0000 0xe00f_ffff CCSR 1M - *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M - *5) 0xc000_0000 0xdfff_ffff SRIO 512MB - *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB - *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB - *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB - *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB - *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB - * - *Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - -#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - -#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ -#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long (4f-3f)/8 -3: - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6 -4: - entry_end |
