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authorMingkai Hu <Mingkai.Hu@freescale.com>2015-10-26 19:47:52 +0800
committerYork Sun <yorksun@freescale.com>2015-10-29 10:34:01 -0700
commitf3a8e2b7d41ca9039e934b5a59899dd57c577fa3 (patch)
tree7ef53f37bd79d91736b251bb49dde1354016b46a /board/freescale/ls1043ardb/cpld.c
parent8281c58fd46d095e28e60b2fb0ce84b4444896f8 (diff)
downloadtalos-obmc-uboot-f3a8e2b7d41ca9039e934b5a59899dd57c577fa3.tar.gz
talos-obmc-uboot-f3a8e2b7d41ca9039e934b5a59899dd57c577fa3.zip
armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Diffstat (limited to 'board/freescale/ls1043ardb/cpld.c')
-rw-r--r--board/freescale/ls1043ardb/cpld.c115
1 files changed, 115 insertions, 0 deletions
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
new file mode 100644
index 0000000000..3f1101ed7c
--- /dev/null
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale LS1043ARDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg7 = CPLD_READ(vbank);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+
+ reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
+ CPLD_WRITE(vbank, reg7);
+
+ CPLD_WRITE(system_rst, 1);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+ CPLD_WRITE(global_rst, 1);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
+ printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
+ printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
+ printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
+ printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
+ printf("vbank = %x\n", CPLD_READ(vbank));
+ printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
+ printf("uart_sel = %x\n", CPLD_READ(uart_sel));
+ printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
+ printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
+ printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
+ printf("status_led = %x\n", CPLD_READ(status_led));
+ putc('\n');
+}
+#endif
+
+void cpld_rev_bit(unsigned char *value)
+{
+ u8 rev_val, val;
+ int i;
+
+ val = *value;
+ rev_val = val & 1;
+ for (i = 1; i <= 7; i++) {
+ val >>= 1;
+ rev_val <<= 1;
+ rev_val |= val & 1;
+ }
+
+ *value = rev_val;
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset: reset to default bank\n"
+ "cpld reset altbank: reset to alternate bank\n"
+#ifdef DEBUG
+ "cpld dump - display the CPLD registers\n"
+#endif
+);
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