diff options
| author | Alison Wang <b18965@freescale.com> | 2015-03-12 11:31:44 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-21 10:19:19 -0700 |
| commit | 036f3f3379d56a4eb64d5154b47a8981a478fe3e (patch) | |
| tree | aeea3c64015236dca6ed8a7ab3b74b9f61e1962d /board/freescale/ls1021atwr/ls1021atwr.c | |
| parent | d77447fdb122dab290fb1ad184a62456011e6e06 (diff) | |
| download | talos-obmc-uboot-036f3f3379d56a4eb64d5154b47a8981a478fe3e.tar.gz talos-obmc-uboot-036f3f3379d56a4eb64d5154b47a8981a478fe3e.zip | |
arm/ls102xa:Add support of conditional workaround implementation as per SoC ver
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1021atwr/ls1021atwr.c')
| -rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 27 |
1 files changed, 21 insertions, 6 deletions
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index fb8525fe59..a9c87f2a22 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -122,6 +122,17 @@ int checkboard(void) return 0; } +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -264,6 +275,7 @@ int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); @@ -289,12 +301,15 @@ int board_early_init_f(void) out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + } return 0; } |
