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| author | York Sun <yorksun@freescale.com> | 2014-09-11 13:32:07 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 09:12:12 -0700 |
| commit | c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76 (patch) | |
| tree | 1a521d509a9752c0f279416c7d54c98c1d854068 /board/freescale/ls1021aqds/ddr.h | |
| parent | f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb (diff) | |
| download | talos-obmc-uboot-c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76.tar.gz talos-obmc-uboot-c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76.zip | |
board/ls1021aqds: Add DDR4 support
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Diffstat (limited to 'board/freescale/ls1021aqds/ddr.h')
| -rw-r--r-- | board/freescale/ls1021aqds/ddr.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index 16d87cbe82..f819c99dba 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -30,6 +30,13 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, @@ -39,6 +46,9 @@ static const struct board_specific_parameters udimm0[] = { {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif {} }; |
