powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)

The P3041DS & P5020DS boards are almost identical (except for the
processor in them).  Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.

Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS.  We utilize some of these for SERDES clock
configuration.

Additionally, the P3041DS/P5020DS support NAND.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

6 files changed, 87 insertions, 7 deletions

diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 1047d783f4..69e81a4d36 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -28,7 +28,9 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS-y	+= $(BOARD).o
 COBJS-y	+= ddr.o
+COBJS-$(CONFIG_P3041DS)	+= p3041ds_ddr.o
 COBJS-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
+COBJS-$(CONFIG_P5020DS)	+= p5020ds_ddr.o
 COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 3db93c3644..93241251b8 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -87,10 +87,21 @@ int checkboard (void)
 	 * don't match.
 	 */
 	puts("SERDES Reference Clocks: ");
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+	sw = in_8(&PIXIS_SW(5));
+	for (i = 0; i < 3; i++) {
+		static const char *freq[] = {"100", "125", "156.25", "212.5" };
+		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+
+		printf("Bank%u=%sMhz ", i+1, freq[clock]);
+	}
+	puts("\n");
+#else
 	sw = in_8(&PIXIS_SW(3));
 	printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
 	printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
 	printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
+#endif
 
 	return 0;
 }
@@ -146,7 +157,7 @@ static const char *serdes_clock_to_string(u32 clock)
 	case SRDS_PLLCR0_RFCK_SEL_156_25:
 		return "156.25";
 	default:
-		return "???";
+		return "150";
 	}
 }
 
@@ -157,19 +168,41 @@ int misc_init_r(void)
 	serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 	u32 actual[NUM_SRDS_BANKS];
 	unsigned int i;
-	u8 sw3;
+	u8 sw;
 
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+	sw = in_8(&PIXIS_SW(5));
+	for (i = 0; i < 3; i++) {
+		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 2:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		default:
+			printf("Warning: SDREFCLK%u switch setting of '11' is "
+			       "unsupported\n", i + 1);
+			break;
+		}
+	}
+#else
 	/* Warn if the expected SERDES reference clocks don't match the
 	 * actual reference clocks.  This needs to be done after calling
 	 * p4080_erratum_serdes8(), since that function may modify the clocks.
 	 */
-	sw3 = in_8(&PIXIS_SW(3));
-	actual[0] = (sw3 & 0x40) ?
+	sw = in_8(&PIXIS_SW(3));
+	actual[0] = (sw & 0x40) ?
 		SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
-	actual[1] = (sw3 & 0x20) ?
+	actual[1] = (sw & 0x20) ?
 		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
-	actual[2] = (sw3 & 0x10) ?
+	actual[2] = (sw & 0x10) ?
 		SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+#endif
 
 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
 		u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c
index 43b4b97de1..d2ba556b63 100644
--- a/board/freescale/corenet_ds/law.c
+++ b/board/freescale/corenet_ds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -35,6 +35,9 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
new file mode 100644
index 0000000000..5a8ed94b04
--- /dev/null
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
new file mode 100644
index 0000000000..e65de364d7
--- /dev/null
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+	{0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index fe77e798a8..38736b4496 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -117,6 +117,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_4M, 1),
 #endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 16, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);