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authorKumar Gala <galak@kernel.crashing.org>2010-05-21 03:02:16 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 10:55:08 -0500
commitebf9d5261efc7a60eac54b675b67e3c7ab614f60 (patch)
treebbf3e11442008d74cef1194eab3a7d773d2b6304 /board/freescale/common
parentb4a60e521c66b1e634cacdebcfae3a1e1c9deb52 (diff)
downloadtalos-obmc-uboot-ebf9d5261efc7a60eac54b675b67e3c7ab614f60.tar.gz
talos-obmc-uboot-ebf9d5261efc7a60eac54b675b67e3c7ab614f60.zip
Move ICS CLK chip frequency calculation code into a common board library
We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'board/freescale/common')
-rw-r--r--board/freescale/common/Makefile1
-rw-r--r--board/freescale/common/ics307_clk.c88
-rw-r--r--board/freescale/common/ics307_clk.h30
3 files changed, 119 insertions, 0 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index df289aa634..d18445be64 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
+COBJS-$(CONFIG_P2020DS) += ics307_clk.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c
new file mode 100644
index 0000000000..89d8810f74
--- /dev/null
+++ b/board/freescale/common/ics307_clk.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "ics307_clk.h"
+
+#ifdef CONFIG_FSL_NGPIXIS
+#include "ngpixis.h"
+#else
+#include "pixis.h"
+#endif
+
+/* decode S[0-2] to Output Divider (OD) */
+static u8 ics307_s_to_od[] = {
+ 10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/*
+ * Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it.
+ */
+static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
+{
+ const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+ unsigned long rdw = cw2 & 0x7F;
+ unsigned long od = ics307_s_to_od[cw0 & 0x7];
+ unsigned long freq;
+
+ /*
+ * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
+ *
+ * cw0: C1 C0 TTL F1 F0 S2 S1 S0
+ * cw1: V8 V7 V6 V5 V4 V3 V2 V1
+ * cw2: V0 R6 R5 R4 R3 R2 R1 R0
+ *
+ * R6:R0 = Reference Divider Word (RDW)
+ * V8:V0 = VCO Divider Word (VDW)
+ * S2:S0 = Output Divider Select (OD)
+ * F1:F0 = Function of CLK2 Output
+ * TTL = duty cycle
+ * C1:C0 = internal load capacitance for cyrstal
+ *
+ */
+
+ freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
+
+ debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+ freq);
+ return freq;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return ics307_clk_freq(
+ in_8(&pixis->sclk[0]),
+ in_8(&pixis->sclk[1]),
+ in_8(&pixis->sclk[2]));
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return ics307_clk_freq(
+ in_8(&pixis->dclk[0]),
+ in_8(&pixis->dclk[1]),
+ in_8(&pixis->dclk[2]));
+}
diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h
new file mode 100644
index 0000000000..db3dbc41f7
--- /dev/null
+++ b/board/freescale/common/ics307_clk.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ICS_CLK_H_
+#define __ICS_CLK_H_ 1
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(void);
+extern unsigned long get_board_ddr_clk(void);
+#endif
+
+#endif /* __ICS_CLK_H_ */
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