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| author | Grzegorz Bernacki <gjb@semihalf.com> | 2007-10-01 09:51:50 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-10-02 11:30:37 +0200 |
| commit | 2db64784061bfc34f4ba70ef1d2fbe7133b55670 (patch) | |
| tree | 52999ea19bebedc4e20b02c431fe759e391a0873 /board/amcc | |
| parent | 636538c520ed118e5e50f592250232a5f943fb84 (diff) | |
| download | talos-obmc-uboot-2db64784061bfc34f4ba70ef1d2fbe7133b55670.tar.gz talos-obmc-uboot-2db64784061bfc34f4ba70ef1d2fbe7133b55670.zip | |
Program EPLD to force full duplex mode for PHY.
EPLD forces modes of PHY operation. By default full duplex is turned off.
This fix turns it on.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Diffstat (limited to 'board/amcc')
| -rw-r--r-- | board/amcc/luan/luan.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 7b16f8a39a..1bd7efa0ba 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); @@ -66,8 +64,6 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ - return 0; } @@ -79,7 +75,18 @@ int board_early_init_f(void) int misc_init_r(void) { volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ + + /* set modes of operation */ + x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | + EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; + /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ + x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; + + /* put Ethernet+PHY in reset */ + x->ethuart &= ~EPLD2_RESET_ETH_N; + udelay(10000); + /* take Ethernet+PHY out of reset */ + x->ethuart |= EPLD2_RESET_ETH_N; return 0; } |
