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| author | Marek Vasut <marex@denx.de> | 2015-08-10 21:24:53 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-23 11:56:19 +0200 |
| commit | f089240128329fe6a49a5272aef732b47613c2f5 (patch) | |
| tree | 40fb3564ff53efcf82d58774547db091e9f4aa6f /board/altera/arria5-socdk/qts/iocsr_config.h | |
| parent | cd9b73177100598e7be0a9033a4a2ed4a7d24fbb (diff) | |
| download | talos-obmc-uboot-f089240128329fe6a49a5272aef732b47613c2f5.tar.gz talos-obmc-uboot-f089240128329fe6a49a5272aef732b47613c2f5.zip | |
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.
On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/altera/arria5-socdk/qts/iocsr_config.h')
| -rw-r--r-- | board/altera/arria5-socdk/qts/iocsr_config.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h new file mode 100644 index 0000000000..d1c9b0d36a --- /dev/null +++ b/board/altera/arria5-socdk/qts/iocsr_config.h @@ -0,0 +1,26 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_IOCSR_CONFIG_H_ +#define _PRELOADER_IOCSR_CONFIG_H_ + +#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#endif + +#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ |
