Merge branch 'master' of git://git.denx.de/u-boot-arm

39 files changed, 493 insertions, 383 deletions

diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 8b631920c9..494768edfb 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -235,8 +235,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -355,8 +355,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index e5e7913d94..6277ae0921 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -284,8 +284,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -500,8 +500,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 #ifdef CONFIG_ENABLE_MMU
@@ -559,7 +559,7 @@ clbss_l:
 	str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 #ifndef CONFIG_NAND_SPL
 	ldr	pc, _start_armboot
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 0f5f6c4611..6a8d57b09c 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -201,8 +201,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -318,8 +318,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
@@ -342,7 +342,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index a079bb2727..09ee815270 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -246,8 +246,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -406,8 +406,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -429,7 +429,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
index c0a856dfe1..f173400ac3 100644
--- a/arch/arm/cpu/arm925t/start.S
+++ b/arch/arm/cpu/arm925t/start.S
@@ -238,8 +238,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -377,8 +377,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -400,7 +400,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c
index 141a7d1ec6..5e30f1dccc 100644
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ b/arch/arm/cpu/arm926ejs/at91/cpu.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
  * (C) Copyright 2009
  * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
@@ -22,12 +24,11 @@
  */
 
 #include <common.h>
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy SoC access. Please update!
-#endif
 
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/io.h>
 
@@ -35,18 +36,26 @@
 #define CONFIG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
-/*
- * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
- * to keep track of the bootcount.
- */
-#define AT91_GPBR_BOOTCOUNT_REGISTER 3
-#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
-
 int arch_cpu_init(void)
 {
 	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
 }
 
+void arch_preboot_os(void)
+{
+	ulong cpiv;
+	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
+
+	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+	/*
+	 * Disable PITC
+	 * Add 0x1000 to current counter to stop it faster
+	 * without waiting for wrapping back to 0
+	 */
+	writel(cpiv + 0x1000, &pit->mr);
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
@@ -66,27 +75,26 @@ int print_cpuinfo(void)
 
 #ifdef CONFIG_BOOTCOUNT_LIMIT
 /*
- * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
- * in one 32-bit register. This is done, as the AT91SAM9260 only has
- * 4 GPBR.
+ * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register.
+ * This is done so we need to use only one of the four GPBR registers.
  */
 void bootcount_store (ulong a)
 {
-	volatile ulong *save_addr =
-		(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+	at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
 
-	*save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
+	writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff),
+		&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
 }
 
 ulong bootcount_load (void)
 {
-	volatile ulong *save_addr =
-		(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+	at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
 
-	if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+	ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
+	if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
 		return 0;
 	else
-		return (*save_addr & 0x0000ffff);
+		return val & 0x0000ffff;
 }
 
 #endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 82c978bd93..b4a4c0428f 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -54,10 +54,11 @@ unsigned char get_random_hex(void)
 	u8 outbuf[BUFLEN];
 
 	/*
-	 * in case of 88F6281/88F6192 A0,
+	 * in case of 88F6281/88F6282/88F6192 A0,
 	 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
-	 * Does not have names at this moment (no errata available)
+	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
+	 * reserved regs and does not have names at this moment
+	 * (no errata available)
 	 */
 	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
 	for (i = 0; i < BUFLEN; i++) {
@@ -271,20 +272,31 @@ static void kw_sysrst_check(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	char *name = "Unknown";
+	char *rev;
+	u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
 
-	switch (readl(KW_REG_DEVICE_ID) & 0x03) {
-	case 1:
-		name = "88F6192_A0";
+	if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
+		printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case 0:
+		rev = "Z0";
 		break;
 	case 2:
-		name = "88F6281_A0";
+		rev = "A0";
+		break;
+	case 3:
+		rev = "A1";
 		break;
 	default:
-		printf("SoC:   Unsupported Kirkwood\n");
-		return -1;
+		rev = "??";
+		break;
 	}
-	printf("SoC:   Kirkwood %s\n", name);
+
+	printf("SoC:   Kirkwood 88F%04x_%s\n", devid, rev);
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
index 8f2a18af6b..7439c87f68 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -23,8 +23,11 @@
  */
 
 #include <config.h>
+#include <common.h>
 #include <asm/arch/kirkwood.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define KW_REG_CPUCS_WIN_BAR(x)		(KW_REGISTER(0x1500) + (x * 0x08))
 #define KW_REG_CPUCS_WIN_SZ(x)		(KW_REGISTER(0x1504) + (x * 0x08))
 /*
@@ -56,3 +59,38 @@ u32 kw_sdram_bs(enum memory_bank bank)
 	result += 0x01000000;
 	return result;
 }
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
+
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 260f88b46e..1894b52fbf 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -48,24 +48,34 @@ void reset_cpu(unsigned long ignored)
 }
 
 /*
- * Window Size
+ * Compute Window Size field value from size expressed in bytes
  * Used with the Base register to set the address window size and location.
  * Must be programmed from LSB to MSB as sequence of ones followed by
  * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
+ * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
+ * NOTES:
+ * 1) A sizeval equal to 0x0 specifies 4 GiB.
+ * 2) A return value of 0x0 specifies 64 KiB.
  */
 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
 {
-	int i;
-	unsigned int j = 0;
-	u32 val = sizeval >> 1;
-
-	for (i = 0; val >= 0x10000; i++) {
-		j |= (1 << i);
-		val = val >> 1;
-	}
-	return 0x0000ffff & j;
+	/*
+	 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
+	 * For sizeval > 0 this is equivalent to:
+	 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
+	 */
+	sizeval = (sizeval - 1) >> 16;
+
+	/*
+	 * Propagate 'one' bits to the right by 'oring' them.
+	 * We need only treat bits 15-0.
+	 */
+	sizeval |= sizeval >> 1;  /* 'Or' bit 15 onto bit 14 */
+	sizeval |= sizeval >> 2;  /* 'Or' bits 15-14 onto bits 13-12 */
+	sizeval |= sizeval >> 4;  /* 'Or' bits 15-12 onto bits 11-8 */
+	sizeval |= sizeval >> 8;  /* 'Or' bits 15-8 onto bits 7-0*/
+
+	return sizeval;
 }
 
 /*
@@ -77,6 +87,17 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
  *
  * If remap function not used, remap_lo must be set as base
  *
+ * NOTES:
+ *
+ * 1) in order to avoid windows with inconsistent control and base values
+ *    (which could prevent access to BOOTCS and hence execution from FLASH)
+ *    always disable window before writing the base value then reenable it
+ *    by writing the control value.
+ *
+ * 2) in order to avoid losing access to BOOTCS when disabling window 7,
+ *    first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
+ *    then configure windows 6 for its own target.
+ *
  * Reference Documentation:
  * Mbus-L to Mbus Bridge Registers Configuration.
  * (Sec 25.1 and 25.3 of Datasheet)
@@ -86,57 +107,64 @@ int orion5x_config_adr_windows(void)
 	struct orion5x_win_registers *winregs =
 		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
 
-	/* Window 0: PCIE MEM address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
-		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
-		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 0, configure it for its intended target, enable it. */
+	writel(0, &winregs[0].ctrl);
 	writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
 	writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
 	writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
-
-	/* Window 1: PCIE IO address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
-		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
-		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
+		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 1, configure it for its intended target, enable it. */
+	writel(0, &winregs[1].ctrl);
 	writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
 	writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
 	writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
-
-	/* Window 2: PCI MEM address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
+		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+/* Disable window 2, configure it for its intended target, enable it. */
+	writel(0, &winregs[2].ctrl);
+	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
 	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
 		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
 		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
-	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
-
-	/* Window 3: PCI IO address space */
+/* Disable window 3, configure it for its intended target, enable it. */
+	writel(0, &winregs[3].ctrl);
+	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
 	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
 		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
 		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
-	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
-
-	/* Window 4: DEV_CS0 address space */
+/* Disable window 4, configure it for its intended target, enable it. */
+	writel(0, &winregs[4].ctrl);
+	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
 	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
 		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
-	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
-
-	/* Window 5: DEV_CS1 address space */
+/* Disable window 5, configure it for its intended target, enable it. */
+	writel(0, &winregs[5].ctrl);
+	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
 	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
 		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
-	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
-
-	/* Window 6: DEV_CS2 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+/* Disable window 6, configure it for FLASH, enable it. */
+	writel(0, &winregs[6].ctrl);
+	writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
 		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
-
-	/* Window 7: BOOT Memory address space */
+/* Disable window 7, configure it for FLASH, enable it. */
+	writel(0, &winregs[7].ctrl);
+	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
 	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
 		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
-	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
+/* Disable window 6, configure it for its intended target, enable it. */
+	writel(0, &winregs[6].ctrl);
+	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
 
 	return 0;
 }
@@ -265,6 +293,8 @@ int arch_misc_init(void)
 	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
 	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
 
+	/* initialize timer */
+	timer_init_r();
 	return 0;
 }
 #endif /* CONFIG_ARCH_MISC_INIT */
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
index 115448fa3f..089ef47b37 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -173,9 +173,11 @@ int timer_init(void)
 	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
 	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
 	writel(cntmrctrl, CNTMR_CTRL_REG);
+	return 0;
+}
 
+void timer_init_r(void)
+{
 	/* init the timestamp and lastdec value */
 	reset_timer_masked();
-
-	return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 16ee972f2b..a960689e75 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -236,8 +236,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -341,8 +341,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -368,7 +368,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	bl coloured_LED_init
 	bl red_LED_on
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 18ed0b2da4..4f062e5fff 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -207,8 +207,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -309,8 +309,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 	/* Set up the stack						    */
 stack_setup:
diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
index b39fdc64c4..79ef517369 100644
--- a/arch/arm/cpu/arm_intcm/start.S
+++ b/arch/arm/cpu/arm_intcm/start.S
@@ -205,8 +205,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -305,8 +305,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 	/* Set up the stack						    */
 stack_setup:
@@ -327,7 +327,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ae20299db7..7743fefdbe 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,6 +27,7 @@ LIB	= $(obj)lib$(CPU).a
 
 START	:= start.o
 COBJS	:= cpu.o
+COBJS  += syslib.o
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -44,4 +45,4 @@ include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
 
-#########################################################################
\ No newline at end of file
+#########################################################################
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index caee7263b1..aedea7b95b 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,7 +28,6 @@ LIB	= $(obj)libomap-common.a
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
-COBJS	+= syslib.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f411c0f4f0..c392c5d9d6 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -209,8 +209,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -324,8 +324,8 @@ relocate:				@ relocate U-Boot to RAM
 copy_loop:				@ copy 32 bytes at a time
 	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
 	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
-	cmp	r0, r2			@ until source end addreee [r2]
-	ble	copy_loop
+	cmp	r0, r2			@ until source end address [r2]
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack */
diff --git a/arch/arm/cpu/armv7/omap-common/syslib.c b/arch/arm/cpu/armv7/syslib.c
index f9ed9a307b..f9ed9a307b 100644
--- a/arch/arm/cpu/armv7/omap-common/syslib.c
+++ b/arch/arm/cpu/armv7/syslib.c
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
index b2c8255141..940d45d732 100644
--- a/arch/arm/cpu/ixp/start.S
+++ b/arch/arm/cpu/ixp/start.S
@@ -330,8 +330,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -547,8 +547,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -570,7 +570,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
index 002116a401..b8cf1b8b37 100644
--- a/arch/arm/cpu/lh7a40x/start.S
+++ b/arch/arm/cpu/lh7a40x/start.S
@@ -219,8 +219,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -341,9 +341,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	blt	copy_loop		/* a 'ble' here actually copies     */
-					/*   four bytes of bss              */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -367,7 +366,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 064ddbcf3f..cfb94112d0 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -204,8 +204,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -310,7 +310,7 @@ copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
 	cmp	r0, r2			/* until source end address [r2]    */
-	ble	copy_loop
+	blo	copy_loop
 #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -337,7 +337,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 #endif
 
 	ldr	pc, _start_armboot
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
index e1ab5ccb36..c5a67dc66d 100644
--- a/arch/arm/cpu/s3c44b0/start.S
+++ b/arch/arm/cpu/s3c44b0/start.S
@@ -191,8 +191,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -225,7 +225,7 @@ vector_copy_loop:
 	ldmia	r0!, {r3-r10}
 	stmia	r1!, {r3-r10}
 	cmp	r0, r2
-	ble	vector_copy_loop
+	blo	vector_copy_loop
 #endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
@@ -310,8 +310,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 /*
 	now copy to sram the interrupt vector
@@ -324,7 +324,7 @@ vector_copy_loop:
 	ldmia	r0!, {r3-r10}
 	stmia	r1!, {r3-r10}
 	cmp	r0, r2
-	ble	vector_copy_loop
+	blo	vector_copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 4730e5a9ab..d1262ada2c 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -195,8 +195,8 @@ stack_setup:
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
 	/* fix got entries */
@@ -293,8 +293,8 @@ relocate:				/* relocate U-Boot to RAM	    */
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
 #endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
@@ -316,7 +316,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	ble	clbss_l
+	blo	clbss_l
 
 	ldr	pc, _start_armboot
 
diff --git a/arch/arm/include/asm/arch-arm925t/sizes.h b/arch/arm/include/asm/arch-arm925t/sizes.h
deleted file mode 100644
index 7319bd9227..0000000000
--- a/arch/arm/include/asm/arch-arm925t/sizes.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- *		   from .s file by awk -f s2h.awk
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h			1
-
-/* handy sizes */
-#define SZ_1K				0x00000400
-#define SZ_4K				0x00001000
-#define SZ_8K				0x00002000
-#define SZ_16K				0x00004000
-#define SZ_64K				0x00010000
-#define SZ_128K				0x00020000
-#define SZ_256K				0x00040000
-#define SZ_512K				0x00080000
-
-#define SZ_1M				0x00100000
-#define SZ_2M				0x00200000
-#define SZ_4M				0x00400000
-#define SZ_8M				0x00800000
-#define SZ_16M				0x01000000
-#define SZ_32M				0x02000000
-#define SZ_64M				0x04000000
-#define SZ_128M				0x08000000
-#define SZ_256M				0x10000000
-#define SZ_512M				0x20000000
-
-#define SZ_1G				0x40000000
-#define SZ_2G				0x80000000
-
-#endif	/* __sizes_h */
diff --git a/arch/arm/include/asm/arch-arm926ejs/sizes.h b/arch/arm/include/asm/arch-arm926ejs/sizes.h
deleted file mode 100644
index ef0b99b946..0000000000
--- a/arch/arm/include/asm/arch-arm926ejs/sizes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
- * USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- *		   from .s file by awk -f s2h.awk
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h			1
-
-/* handy sizes */
-#define SZ_1K		0x00000400
-#define SZ_4K		0x00001000
-#define SZ_8K		0x00002000
-#define SZ_16K		0x00004000
-#define SZ_64K		0x00010000
-#define SZ_128K	0x00020000
-#define SZ_256K	0x00040000
-#define SZ_512K	0x00080000
-
-#define SZ_1M		0x00100000
-#define SZ_2M		0x00200000
-#define SZ_4M		0x00400000
-#define SZ_8M		0x00800000
-#define SZ_16M		0x01000000
-#define SZ_32M		0x02000000
-#define SZ_64M		0x04000000
-#define SZ_128M	0x08000000
-#define SZ_256M	0x10000000
-#define SZ_512M	0x20000000
-
-#define SZ_1G		0x40000000
-#define SZ_2G		0x80000000
-
-#endif	/* __sizes_h */
diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h
new file mode 100644
index 0000000000..4e451675fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/sysctrl.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYSCTRL_H_
+#define _SYSCTRL_H_
+
+/* System controller (SP810) register definitions */
+#define SP810_TIMER0_ENSEL	(1 << 15)
+#define SP810_TIMER1_ENSEL	(1 << 17)
+#define SP810_TIMER2_ENSEL	(1 << 19)
+#define SP810_TIMER3_ENSEL	(1 << 21)
+
+struct sysctrl {
+	u32 scctrl;		/* 0x000 */
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	u32 scperclken;
+	u32 scperstat;
+	u32 res1[0x006];
+	u32 scflashctrl;	/* 0x04c */
+	u32 res2[0x3a4];
+	u32 scsysid0;		/* 0xee0 */
+	u32 scsysid1;
+	u32 scsysid2;
+	u32 scsysid3;
+	u32 scitcr;
+	u32 scitir0;
+	u32 scitir1;
+	u32 scitor;
+	u32 sccntctrl;
+	u32 sccntdata;
+	u32 sccntstep;
+	u32 res3[0x32];
+	u32 scperiphid0;	/* 0xfe0 */
+	u32 scperiphid1;
+	u32 scperiphid2;
+	u32 scperiphid3;
+	u32 scpcellid0;
+	u32 scpcellid1;
+	u32 scpcellid2;
+	u32 scpcellid3;
+};
+#endif /* _SYSCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h
new file mode 100644
index 0000000000..e745e37509
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/systimer.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYSTIMER_H_
+#define _SYSTIMER_H_
+
+/* AMBA timer register base address */
+#define SYSTIMER_BASE		0x10011000
+
+#define SYSHZ_CLOCK		1000000		/* Timers -> 1Mhz */
+#define SYSTIMER_RELOAD		0xFFFFFFFF
+#define SYSTIMER_EN		(1 << 7)
+#define SYSTIMER_32BIT		(1 << 1)
+
+struct systimer {
+	u32 timer0load;		/* 0x00 */
+	u32 timer0value;
+	u32 timer0control;
+	u32 timer0intclr;
+	u32 timer0ris;
+	u32 timer0mis;
+	u32 timer0bgload;
+	u32 timer1load;		/* 0x20 */
+	u32 timer1value;
+	u32 timer1control;
+	u32 timer1intclr;
+	u32 timer1ris;
+	u32 timer1mis;
+	u32 timer1bgload;
+};
+#endif /* _SYSTIMER_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/wdt.h b/arch/arm/include/asm/arch-armv7/wdt.h
new file mode 100644
index 0000000000..ee74c38c19
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/wdt.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2010
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/* Watchdog timer (SP805) register base address */
+#define WDT_BASE	0x100E5000
+
+#define WDT_EN		0x2
+#define WDT_RESET_LOAD	0x0
+
+struct wdt {
+	u32 wdogload;		/* 0x000 */
+	u32 wdogvalue;
+	u32 wdogcontrol;
+	u32 wdogintclr;
+	u32 wdogris;
+	u32 wdogmis;
+	u32 res1[0x2F9];
+	u32 wdoglock;		/* 0xC00 */
+	u32 res2[0xBE];
+	u32 wdogitcr;		/* 0xF00 */
+	u32 wdogitop;
+	u32 res3[0x35];
+	u32 wdogperiphid0;	/* 0xFE0 */
+	u32 wdogperiphid1;
+	u32 wdogperiphid2;
+	u32 wdogperiphid3;
+	u32 wdogpcellid0;
+	u32 wdogpcellid1;
+	u32 wdogpcellid2;
+	u32 wdogpcellid3;
+};
+
+#endif /* _WDT_H_ */
diff --git a/arch/arm/include/asm/arch-at91/at91_emac.h b/arch/arm/include/asm/arch-at91/at91_emac.h
index 45ae33311e..0e2ff78f42 100644
--- a/arch/arm/include/asm/arch-at91/at91_emac.h
+++ b/arch/arm/include/asm/arch-at91/at91_emac.h
@@ -61,7 +61,7 @@ typedef struct at91_emac {
 	u32	 reserved2[3];
 	u32	 hsh;
 	u32	 hsl;
-	u32	 sh1l;
+	u32	 sa1l;
 	u32	 sa1h;
 	u32	 sa2l;
 	u32	 sa2h;
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
index b3022a3780..d28c51a9b6 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -35,6 +35,8 @@
 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
 		((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
 
+#define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
+#define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
 #define KW_REG_DEVICE_ID		(KW_MPP_BASE + 0x34)
 #define KW_REG_SYSRST_CNT		(KW_MPP_BASE + 0x50)
 #define SYSRST_CNT_1SEC_VAL		(25*1000000)
diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h
index d72585c8a0..f05e743d76 100644
--- a/arch/arm/include/asm/arch-mx31/mx31-regs.h
+++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h
@@ -57,6 +57,14 @@ struct clock_control_regs {
 	u32 pdr2;
 };
 
+/* GPIO Registers */
+struct gpio_regs {
+	u32	gpio_dr;
+	u32	gpio_dir;
+	u32	gpio_psr;
+};
+
+
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B	(1 << 31)
 #define CCM_RCSR_NFMS	(1 << 30)
@@ -153,9 +161,9 @@ struct clock_control_regs {
 /*
  * GPIO
  */
-#define GPIO1_BASE	0x53FCC000
-#define GPIO2_BASE	0x53FD0000
-#define GPIO3_BASE	0x53FA4000
+#define GPIO1_BASE_ADDR	0x53FCC000
+#define GPIO2_BASE_ADDR	0x53FD0000
+#define GPIO3_BASE_ADDR	0x53FA4000
 #define GPIO_DR		0x00000000	/* data register */
 #define GPIO_GDIR	0x00000004	/* direction register */
 #define GPIO_PSR	0x00000008	/* pad status register */
diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h
index f702d260f1..5a5aa114a7 100644
--- a/arch/arm/include/asm/arch-mx31/mx31.h
+++ b/arch/arm/include/asm/arch-mx31/mx31.h
@@ -28,31 +28,6 @@ extern u32 mx31_get_ipg_clk(void);
 #define imx_get_uartclk mx31_get_ipg_clk
 extern void mx31_gpio_mux(unsigned long mode);
 
-enum mx31_gpio_direction {
-	MX31_GPIO_DIRECTION_IN,
-	MX31_GPIO_DIRECTION_OUT,
-};
-
-#ifdef CONFIG_MX31_GPIO
-extern int mx31_gpio_direction(unsigned int gpio,
-			       enum mx31_gpio_direction direction);
-extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
-extern int mx31_gpio_get(unsigned int gpio);
-#else
-static inline int mx31_gpio_direction(unsigned int gpio,
-				      enum mx31_gpio_direction direction)
-{
-	return 1;
-}
-static inline int mx31_gpio_get(unsigned int gpio)
-{
-	return 1;
-}
-static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
-{
-}
-#endif
-
 void mx31_uart1_hw_init(void);
 void mx31_spi2_hw_init(void);
 
diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h
index 3887d3cec4..3ddda401f3 100644
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx51/imx-regs.h
@@ -23,9 +23,6 @@
 #ifndef __ASM_ARCH_MXC_MX51_H__
 #define __ASM_ARCH_MXC_MX51_H__
 
-#define __REG(x)	(*((volatile u32 *)(x)))
-#define __REG16(x)	(*((volatile u16 *)(x)))
-#define __REG8(x)	(*((volatile u8 *)(x)))
 /*
  * IRAM
  */
@@ -207,7 +204,12 @@
 #define BOARD_REV_1_0           0x0
 #define BOARD_REV_2_0           0x1
 
-#ifndef __ASSEMBLY__
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+#define __REG(x)	(*((volatile u32 *)(x)))
+#define __REG16(x)	(*((volatile u16 *)(x)))
+#define __REG8(x)	(*((volatile u8 *)(x)))
 
 struct clkctl {
 	u32	ccr;
@@ -256,6 +258,22 @@ struct weim {
 	u32	cswcr2;
 };
 
+/* GPIO Registers */
+struct gpio_regs {
+	u32	gpio_dr;
+	u32	gpio_dir;
+	u32	gpio_psr;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32	scr;
+	u32	sbmr;
+	u32	srsr;
+	u32	reserved1[2];
+	u32	sisr;
+	u32	simr;
+};
 #endif /* __ASSEMBLER__*/
 
 #endif				/*  __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h
index ca26f4166b..b44ff252bf 100644
--- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
+++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h
@@ -368,6 +368,50 @@ enum iomux_pins {
 	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
 	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
 	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+
+	/* The following are PADS used for drive strength */
+
+	MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
+	MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
+	MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
+	MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
+	MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
+	MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
+	MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
+	MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
+	MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
+	MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
+	MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
+	MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
+	MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
+	MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
+	MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
+	MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
+	MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
+	MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
+	MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
+	MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
+	MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
+	MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
+	MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
+	MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
+	MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
+	MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
+	MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
+	MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
+	MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
+	MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
+	MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
+	MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
+	MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
+	MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
+	MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
+	MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
+	MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
+	MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
+	MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
+	MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
+	MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
 };
 
 #endif				/* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h
index bf500a8b32..f687503cad 100644
--- a/arch/arm/include/asm/arch-mx51/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx51/sys_proto.h
@@ -26,5 +26,6 @@
 
 u32 get_cpu_rev(void);
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+void sdelay(unsigned long);
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap/sizes.h b/arch/arm/include/asm/arch-omap/sizes.h
deleted file mode 100644
index f8d92ca120..0000000000
--- a/arch/arm/include/asm/arch-omap/sizes.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- *                 from .s file by awk -f s2h.awk
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h                       1
-
-/* handy sizes */
-#define SZ_1K                           0x00000400
-#define SZ_4K                           0x00001000
-#define SZ_8K                           0x00002000
-#define SZ_16K                          0x00004000
-#define SZ_64K                          0x00010000
-#define SZ_128K                         0x00020000
-#define SZ_256K                         0x00040000
-#define SZ_512K                         0x00080000
-
-#define SZ_1M                           0x00100000
-#define SZ_2M                           0x00200000
-#define SZ_4M                           0x00400000
-#define SZ_8M                           0x00800000
-#define SZ_16M                          0x01000000
-#define SZ_32M                          0x02000000
-#define SZ_64M                          0x04000000
-#define SZ_128M                         0x08000000
-#define SZ_256M                         0x10000000
-#define SZ_512M                         0x20000000
-
-#define SZ_1G                           0x40000000
-#define SZ_2G                           0x80000000
-
-#endif
-
-/*         END */
diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h
index 0c11beccf6..6032419641 100644
--- a/arch/arm/include/asm/arch-omap24xx/omap2420.h
+++ b/arch/arm/include/asm/arch-omap24xx/omap2420.h
@@ -25,7 +25,7 @@
 #ifndef _OMAP2420_SYS_H_
 #define _OMAP2420_SYS_H_
 
-#include <asm/arch/sizes.h>
+#include <asm/sizes.h>
 
 /*
  * 2420 specific Section
diff --git a/arch/arm/include/asm/arch-omap24xx/sizes.h b/arch/arm/include/asm/arch-omap24xx/sizes.h
deleted file mode 100644
index aaba18f150..0000000000
--- a/arch/arm/include/asm/arch-omap24xx/sizes.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h			1
-
-/* handy sizes */
-#define SZ_1K				0x00000400
-#define SZ_4K				0x00001000
-#define SZ_8K				0x00002000
-#define SZ_16K				0x00004000
-#define SZ_32K				0x00008000
-#define SZ_64K				0x00010000
-#define SZ_128K				0x00020000
-#define SZ_256K				0x00040000
-#define SZ_512K				0x00080000
-
-#define SZ_1M				0x00100000
-#define SZ_2M				0x00200000
-#define SZ_4M				0x00400000
-#define SZ_8M				0x00800000
-#define SZ_16M				0x01000000
-#define SZ_31M				0x01F00000
-#define SZ_32M				0x02000000
-#define SZ_64M				0x04000000
-#define SZ_128M				0x08000000
-#define SZ_256M				0x10000000
-#define SZ_512M				0x20000000
-
-#define SZ_1G				0x40000000
-#define SZ_2G				0x80000000
-
-#endif	/* __sizes_h */
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
index 6ce02a9212..c84efaf02b 100644
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -255,5 +255,6 @@ void reset_cpu(unsigned long ignored);
 u32 orion5x_device_id(void);
 u32 orion5x_device_rev(void);
 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+void timer_init_r(void);
 #endif /* __ASSEMBLY__ */
 #endif /* _ORION5X_CPU_H */
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index f8d92ca120..b0b4f6af61 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -13,9 +13,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-/* DO NOT EDIT!! - this file automatically generated
- *                 from .s file by awk -f s2h.awk
- */
 /*  Size defintions
  *  Copyright (C) ARM Limited 1998. All rights reserved.
  */
@@ -28,6 +25,7 @@
 #define SZ_4K                           0x00001000
 #define SZ_8K                           0x00002000
 #define SZ_16K                          0x00004000
+#define SZ_32K                          0x00008000
 #define SZ_64K                          0x00010000
 #define SZ_128K                         0x00020000
 #define SZ_256K                         0x00040000
@@ -38,6 +36,7 @@
 #define SZ_4M                           0x00400000
 #define SZ_8M                           0x00800000
 #define SZ_16M                          0x01000000
+#define SZ_31M                          0x01F00000
 #define SZ_32M                          0x02000000
 #define SZ_64M                          0x04000000
 #define SZ_128M                         0x08000000