Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

16 files changed, 805 insertions, 133 deletions

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 79ae883b13..b1b0c710ae 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -9,6 +9,43 @@
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+	SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+	SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+	SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+	SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
+struct smmu_stream_id dev_stream_id[] = {
+	{ 0x100, 0x01, "ETSEC MAC1" },
+	{ 0x104, 0x02, "ETSEC MAC2" },
+	{ 0x108, 0x03, "ETSEC MAC3" },
+	{ 0x10c, 0x04, "PEX1" },
+	{ 0x110, 0x05, "PEX2" },
+	{ 0x114, 0x06, "qDMA" },
+	{ 0x118, 0x07, "SATA" },
+	{ 0x11c, 0x08, "USB3" },
+	{ 0x120, 0x09, "QE" },
+	{ 0x124, 0x0a, "eSDHC" },
+	{ 0x128, 0x0b, "eMA" },
+	{ 0x14c, 0x0c, "2D-ACE" },
+	{ 0x150, 0x0d, "USB2" },
+	{ 0x18c, 0x0e, "DEBUG" },
+};
 
 unsigned int get_soc_major_rev(void)
 {
@@ -88,3 +125,14 @@ int arch_soc_init(void)
 
 	return 0;
 }
+
+int ls102xa_smmu_stream_id_init(void)
+{
+	ls1021x_config_caam_stream_id(sec_liodn_tbl,
+				      ARRAY_SIZE(sec_liodn_tbl));
+
+	ls102xa_config_smmu_stream_id(dev_stream_id,
+				      ARRAY_SIZE(dev_stream_id));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4e4861d107..9c18fd7a16 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -14,6 +14,9 @@
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+#include <fsl_fman.h>
+#endif
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
@@ -204,4 +207,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_LSCH3
 	fdt_fixup_smmu(blob);
 #endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_firmware(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7ff01481be..213ce3a824 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -213,6 +213,24 @@ static void erratum_a009929(void)
 #endif
 }
 
+/*
+ * This erratum requires setting a value to eddrtqcr1 to optimal
+ * the DDR performance. The eddrtqcr1 register is in SCFG space
+ * of LS1043A and the offset is 0x157_020c.
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+	&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+#error A009660 and A008514 can not be both enabled.
+#endif
+
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+	u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+	out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void)
 
 	/* Erratum */
 	erratum_a009929();
+	erratum_a009660();
 }
 #endif
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b574284262..578038be21 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,8 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
-dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
+	ls1021a-qds-lpuart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb
diff --git a/arch/arm/dts/ls1021a-qds-duart.dts b/arch/arm/dts/ls1021a-qds-duart.dts
new file mode 100644
index 0000000000..bc568673ce
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a QDS board common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+	};
+};
diff --git a/arch/arm/dts/ls1021a-qds-lpuart.dts b/arch/arm/dts/ls1021a-qds-lpuart.dts
new file mode 100644
index 0000000000..1d16ffd975
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a QDS board common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-qds.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &lpuart0;
+	};
+};
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dtsi
index e634292359..ca9e835a06 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dtsi
@@ -1,12 +1,11 @@
 /*
- * Freescale ls1021a QDS board device tree source
+ * Freescale ls1021a QDS board common device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/dts-v1/;
 #include "ls1021a.dtsi"
 
 / {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ff3b1bee3e..0ef7c9dd95 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -177,6 +177,8 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A009660
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
index f10cb91f4b..a354684bcc 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -9,4 +9,6 @@
 
 unsigned int get_soc_major_rev(void);
 int arch_soc_init(void);
+int ls102xa_smmu_stream_id_init(void);
+
 #endif /* __FSL_LS102XA_SOC_H */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 80bbc1805f..f168375b45 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,10 @@
 #ifdef CONFIG_FSL_CAAM
 #include <fsl_sec.h>
 #endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include <asm/fsl_pamu.h>
+#include <fsl_secboot_err.h>
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
@@ -44,7 +48,7 @@
 
 #include "../../../../drivers/block/fsl_sata.h"
 #ifdef CONFIG_U_QE
-#include "../../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -432,8 +436,7 @@ void fsl_erratum_a007212_workaround(void)
 ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
-	(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
@@ -465,12 +468,6 @@ ulong cpu_init_f(void)
 #if defined(CONFIG_SYS_CPC_REINIT_F)
 	disable_cpc_sram();
 #endif
-
-#if defined(CONFIG_FSL_CORENET)
-	/* Put PAMU in bypass mode */
-	out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
 #endif
 
 #ifdef CONFIG_CPM2
@@ -954,6 +951,11 @@ int cpu_init_r(void)
 	fman_enet_init();
 #endif
 
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+	if (pamu_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7270be1b28..ced216c680 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -19,7 +19,9 @@
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
-#include "../../../../drivers/qe/qe.h"		/* For struct qe_firmware */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#include <fsl_fman.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -488,125 +490,6 @@ static void ft_fixup_qe_snum(void *blob)
 }
 #endif
 
-/**
- * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
- *
- * The binding for an Fman firmware node is documented in
- * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt.  This node contains
- * the actual Fman firmware binary data.  The operating system is expected to
- * be able to parse the binary data to determine any attributes it needs.
- */
-#ifdef CONFIG_SYS_DPAA_FMAN
-void fdt_fixup_fman_firmware(void *blob)
-{
-	int rc, fmnode, fwnode = -1;
-	uint32_t phandle;
-	struct qe_firmware *fmanfw;
-	const struct qe_header *hdr;
-	unsigned int length;
-	uint32_t crc;
-	const char *p;
-
-	/* The first Fman we find will contain the actual firmware. */
-	fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
-	if (fmnode < 0)
-		/* Exit silently if there are no Fman devices */
-		return;
-
-	/* If we already have a firmware node, then also exit silently. */
-	if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
-		return;
-
-	/* If the environment variable is not set, then exit silently */
-	p = getenv("fman_ucode");
-	if (!p)
-		return;
-
-	fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16);
-	if (!fmanfw)
-		return;
-
-	hdr = &fmanfw->header;
-	length = be32_to_cpu(hdr->length);
-
-	/* Verify the firmware. */
-	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
-		(hdr->magic[2] != 'F')) {
-		printf("Data at %p is not an Fman firmware\n", fmanfw);
-		return;
-	}
-
-	if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
-		printf("Fman firmware at %p is too large (size=%u)\n",
-		       fmanfw, length);
-		return;
-	}
-
-	length -= sizeof(u32);	/* Subtract the size of the CRC */
-	crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length));
-	if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
-		printf("Fman firmware at %p has invalid CRC\n", fmanfw);
-		return;
-	}
-
-	/* Increase the size of the fdt to make room for the node. */
-	rc = fdt_increase_size(blob, fmanfw->header.length);
-	if (rc < 0) {
-		printf("Unable to make room for Fman firmware: %s\n",
-			fdt_strerror(rc));
-		return;
-	}
-
-	/* Create the firmware node. */
-	fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
-	if (fwnode < 0) {
-		char s[64];
-		fdt_get_path(blob, fmnode, s, sizeof(s));
-		printf("Could not add firmware node to %s: %s\n", s,
-		       fdt_strerror(fwnode));
-		return;
-	}
-	rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware");
-	if (rc < 0) {
-		char s[64];
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add compatible property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-	phandle = fdt_create_phandle(blob, fwnode);
-	if (!phandle) {
-		char s[64];
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add phandle property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-	rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length);
-	if (rc < 0) {
-		char s[64];
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add firmware property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-
-	/* Find all other Fman nodes and point them to the firmware node. */
-	while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) {
-		rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle);
-		if (rc < 0) {
-			char s[64];
-			fdt_get_path(blob, fmnode, s, sizeof(s));
-			printf("Could not add pointer property to node %s: %s\n",
-			       s, fdt_strerror(rc));
-			return;
-		}
-	}
-}
-#else
-#define fdt_fixup_fman_firmware(x)
-#endif
-
 #if defined(CONFIG_PPC_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
@@ -752,7 +635,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	ft_fixup_qe_snum(blob);
 #endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
+#endif
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e3df..c5592cdbb3 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
 obj-$(CONFIG_SYS_SRIO) += srio.o
 obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
 
 endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 0000000000..9421f1ebf6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,433 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/log2.h>
+#include <malloc.h>
+#include <asm/fsl_pamu.h>
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+	if ((val & (val - 1)) == 0)
+		return __ilog2_u64(val);
+	else
+		return  __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+	return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+	/* window size is 2^(WSE+1) bytes */
+	return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+		PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+       /* window count is 2^(WCE+1) bytes */
+	return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+	set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+	set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+	       PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+	set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+	set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+	       PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn      Logical IO device number
+ * @param[in] win_addr   starting address of DSA window
+ * @param[in] win-size   size of DSA window
+ * @param[in] omi        Operation mapping index -- if ~omi == 0 then omi
+				not defined
+ * @param[in] stashid    cache stash id for associated cpu -- if ~stashid == 0
+				then stashid not defined
+ * @param[in] snoopid    snoop id for hardware coherency -- if ~snoopid == 0
+				then snoopid not defined
+ * @param[in] subwin_cnt number of sub-windows
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
+	uint64_t win_size, uint32_t omi,
+	uint32_t snoopid, uint32_t stashid,
+	uint32_t subwin_cnt)
+{
+	struct paace *ppaace;
+
+	if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE)
+		return -1;
+
+	if (win_addr & (win_size - 1))
+		return -2;
+
+	if (liodn > NUM_PPAACT_ENTRIES) {
+		printf("Entries in PPACT not sufficient\n");
+		return -3;
+	}
+
+	ppaace = &ppaact[liodn];
+
+	/* window size is 2^(WSE+1) bytes */
+	set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
+	       map_addrspace_size_to_wse(win_size));
+
+	pamu_setup_default_xfer_to_host_ppaace(ppaace);
+
+	if (sizeof(phys_addr_t) > 4)
+		ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20);
+	else
+		ppaace->wbah = 0;
+
+	set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
+	       (win_addr >> PAMU_PAGE_SHIFT));
+
+	/* set up operation mapping if it's configured */
+	if (omi < OME_NUMBER_ENTRIES) {
+		set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+		ppaace->op_encode.index_ot.omi = omi;
+	} else if (~omi != 0) {
+		return -3;
+	}
+
+	/* configure stash id */
+	if (~stashid != 0)
+		set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
+
+	/* configure snoop id */
+	if (~snoopid != 0)
+		ppaace->domain_attr.to_host.snpid = snoopid;
+
+	if (subwin_cnt) {
+		/* window count is 2^(WCE+1) bytes */
+		set_bf(ppaace->impl_attr, PAACE_IA_WCE,
+		       map_subwindow_cnt_to_wce(subwin_cnt));
+		set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
+		ppaace->fspi = fspi;
+		fspi = fspi + DEFAULT_NUM_SUBWINDOWS - 1;
+	} else {
+		set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
+	}
+
+	asm volatile("sync" : : : "memory");
+	/* Mark the ppace entry valid */
+	ppaace->addr_bitfields |= PAACE_V_VALID;
+	asm volatile("sync" : : : "memory");
+
+	return 0;
+}
+
+static int pamu_config_spaace(uint32_t liodn,
+	uint64_t subwin_size, uint64_t subwin_addr, uint64_t size,
+	uint32_t omi, uint32_t snoopid, uint32_t stashid)
+{
+	struct paace *paace;
+	/* Align start addr of subwin to subwindoe size */
+	uint64_t sec_addr = subwin_addr & ~(subwin_size - 1);
+	uint64_t end_addr = subwin_addr + size;
+	int size_shift = __ilog2_u64(subwin_size);
+	uint64_t win_size = 0;
+	uint32_t index, swse;
+	unsigned long fspi_idx;
+
+	/* Recalculate the size */
+	size = end_addr - sec_addr;
+
+	if (!subwin_size)
+		return -1;
+
+	if (liodn > NUM_PPAACT_ENTRIES) {
+		printf("LIODN No programmed %d > no. of PPAACT entries %d\n",
+		       liodn, NUM_PPAACT_ENTRIES);
+		return -1;
+	}
+
+	while (sec_addr < end_addr) {
+		debug("sec_addr < end_addr is %llx < %llx\n", sec_addr,
+		      end_addr);
+		paace = &ppaact[liodn];
+		if (!paace)
+			return -1;
+		fspi_idx = paace->fspi;
+
+		/* Calculating the win_size here as if we map in index 0,
+			paace entry woudl need to  be programmed for SWSE */
+		win_size = end_addr - sec_addr;
+		win_size = 1 << __ilog2_roundup_64(win_size);
+
+		if (win_size > subwin_size)
+			win_size = subwin_size;
+		else if (win_size < PAMU_PAGE_SIZE)
+			win_size = PAMU_PAGE_SIZE;
+
+		debug("win_size is %llx\n", win_size);
+
+		swse = map_addrspace_size_to_wse(win_size);
+		index = sec_addr >> size_shift;
+
+		if (index == 0) {
+			set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse);
+			set_bf(paace->addr_bitfields, PAACE_AF_AP,
+			       PAACE_AP_PERMS_ALL);
+			sec_addr += subwin_size;
+			continue;
+		}
+
+		paace = sec + fspi_idx + index - 1;
+
+		debug("SPAACT:Writing at location %p, index %d\n", paace,
+		      index);
+
+		pamu_setup_default_xfer_to_host_spaace(paace);
+		set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
+		set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
+
+		/* configure snoop id */
+		if (~snoopid != 0)
+			paace->domain_attr.to_host.snpid = snoopid;
+
+		if (paace->addr_bitfields & PAACE_V_VALID) {
+			debug("Reached overlap condition\n");
+			debug("%d < %d\n", get_bf(paace->win_bitfields,
+						  PAACE_WIN_SWSE), swse);
+			if (get_bf(paace->win_bitfields, PAACE_WIN_SWSE) < swse)
+				set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
+				       swse);
+		} else {
+			set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse);
+		}
+
+		paace->addr_bitfields |= PAACE_V_VALID;
+		sec_addr += subwin_size;
+	}
+
+	return 0;
+}
+
+int pamu_init(void)
+{
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	struct ccsr_pamu *regs;
+	u32 i = 0;
+	u64 ppaact_phys, ppaact_lim, ppaact_size;
+	u64 spaact_phys, spaact_lim, spaact_size;
+
+	ppaact_size = sizeof(struct paace) * NUM_PPAACT_ENTRIES;
+	spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
+
+	/* Allocate space for Primary PAACT Table */
+	ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
+	if (!ppaact)
+		return -1;
+	memset(ppaact, 0, ppaact_size);
+
+	/* Allocate space for Secondary PAACT Table */
+	sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
+	if (!sec)
+		return -1;
+	memset(sec, 0, spaact_size);
+
+	ppaact_phys = virt_to_phys((void *)ppaact);
+	ppaact_lim = ppaact_phys + ppaact_size;
+
+	spaact_phys = (uint64_t)virt_to_phys((void *)sec);
+	spaact_lim = spaact_phys + spaact_size;
+
+	/* Configure all PAMU's */
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		regs = (struct ccsr_pamu *)base_addr;
+
+		out_be32(&regs->ppbah, ppaact_phys >> 32);
+		out_be32(&regs->ppbal, (uint32_t)ppaact_phys);
+
+		out_be32(&regs->pplah, (ppaact_lim) >> 32);
+		out_be32(&regs->pplal, (uint32_t)ppaact_lim);
+
+		if (sec != NULL) {
+			out_be32(&regs->spbah, spaact_phys >> 32);
+			out_be32(&regs->spbal, (uint32_t)spaact_phys);
+			out_be32(&regs->splah, spaact_lim >> 32);
+			out_be32(&regs->splal, (uint32_t)spaact_lim);
+		}
+		asm volatile("sync" : : : "memory");
+
+		base_addr += PAMU_OFFSET;
+	}
+
+	return 0;
+}
+
+void pamu_enable(void)
+{
+	u32 i = 0;
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
+			     PAMU_PCR_PE);
+		asm volatile("sync" : : : "memory");
+		base_addr += PAMU_OFFSET;
+	}
+}
+
+void pamu_reset(void)
+{
+	u32 i  = 0;
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	struct ccsr_pamu *regs;
+
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		regs = (struct ccsr_pamu *)base_addr;
+	/* Clear PPAACT Base register */
+		out_be32(&regs->ppbah, 0);
+		out_be32(&regs->ppbal, 0);
+		out_be32(&regs->pplah, 0);
+		out_be32(&regs->pplal, 0);
+		out_be32(&regs->spbah, 0);
+		out_be32(&regs->spbal, 0);
+		out_be32(&regs->splah, 0);
+		out_be32(&regs->splal, 0);
+
+		clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+		asm volatile("sync" : : : "memory");
+		base_addr += PAMU_OFFSET;
+	}
+}
+
+void pamu_disable(void)
+{
+	u32 i  = 0;
+	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+
+
+	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+		clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+		asm volatile("sync" : : : "memory");
+		base_addr += PAMU_OFFSET;
+	}
+}
+
+
+static uint64_t find_max(uint64_t arr[], int num)
+{
+	int i = 0;
+	int max = 0;
+	for (i = 1 ; i < num; i++)
+		if (arr[max] < arr[i])
+			max = i;
+
+	return arr[max];
+}
+
+static uint64_t find_min(uint64_t arr[], int num)
+{
+	int i = 0;
+	int min = 0;
+	for (i = 1 ; i < num; i++)
+		if (arr[min] > arr[i])
+			min = i;
+
+	return arr[min];
+}
+
+static uint32_t get_win_cnt(uint64_t size)
+{
+	uint32_t win_cnt = DEFAULT_NUM_SUBWINDOWS;
+
+	while (win_cnt && (size/win_cnt) < PAMU_PAGE_SIZE)
+		win_cnt >>= 1;
+
+	return win_cnt;
+}
+
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn)
+{
+	int i = 0;
+	int ret = 0;
+	uint32_t num_sec_windows = 0;
+	uint32_t num_windows = 0;
+	uint64_t min_addr, max_addr;
+	uint64_t size;
+	uint64_t subwin_size;
+	int sizebit;
+
+	min_addr = find_min(tbl->start_addr, num_entries);
+	max_addr = find_max(tbl->end_addr, num_entries);
+	size = max_addr - min_addr + 1;
+
+	if (!size)
+		return -1;
+
+	sizebit = __ilog2_roundup_64(size);
+	size = 1 << sizebit;
+	debug("min start_addr is %llx\n", min_addr);
+	debug("max end_addr is %llx\n", max_addr);
+	debug("size found is  %llx\n", size);
+
+	if (size < PAMU_PAGE_SIZE)
+		size = PAMU_PAGE_SIZE;
+
+	while (1) {
+		min_addr = min_addr & ~(size - 1);
+		if (min_addr + size > max_addr)
+			break;
+		size <<= 1;
+		if (!size)
+			return -1;
+	}
+	debug("PAACT :Base addr is %llx\n", min_addr);
+	debug("PAACT : Size is %llx\n", size);
+	num_windows = get_win_cnt(size);
+	/* For a single window, no spaact entries are required
+	 * sec_sub_window count = 0 */
+	if (num_windows > 1)
+		num_sec_windows = num_windows;
+	else
+		num_sec_windows = 0;
+
+	ret = pamu_config_ppaace(liodn, min_addr,
+			size , -1, -1, -1, num_sec_windows);
+
+	if (ret < 0)
+		return ret;
+
+	debug("configured ppace\n");
+
+	if (num_sec_windows) {
+		subwin_size = size >> count_lsb_zeroes(num_sec_windows);
+		debug("subwin_size is %llx\n", subwin_size);
+
+		for (i = 0; i < num_entries; i++) {
+			ret = pamu_config_spaace(liodn,
+				subwin_size, tbl->start_addr[i] - min_addr,
+				tbl->size[i], -1, -1, -1);
+
+			if (ret < 0)
+				return ret;
+		}
+	}
+
+	return ret;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
new file mode 100644
index 0000000000..26c5ea4fd7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_pamu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
+{
+	int i = 0;
+	int j;
+
+	tbl->start_addr[i] =
+			(uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
+	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
+	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
+
+	i++;
+#ifdef CONFIG_SYS_FLASH_BASE_PHYS
+	tbl->start_addr[i] =
+		(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
+	tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
+	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
+
+	i++;
+#endif
+	debug("PAMU address\t\t\tsize\n");
+	for (j = 0; j < i ; j++)
+		debug("%llx \t\t\t%llx\n",  tbl->start_addr[j],  tbl->size[j]);
+
+	*num_entries = i;
+}
+
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s)
+{
+	struct pamu_addr_tbl tbl;
+	int num_entries = 0;
+	int ret = 0;
+
+	construct_pamu_addr_table(&tbl, &num_entries);
+
+	ret = config_pamu(&tbl, num_entries, liodn_ns);
+	if (ret)
+		return ret;
+
+	ret = config_pamu(&tbl, num_entries, liodn_s);
+	if (ret)
+		return ret;
+
+	return ret;
+}
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
new file mode 100644
index 0000000000..93a7cae972
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PAMU_H
+#define __PAMU_H
+
+#define CONFIG_NUM_PAMU		16
+#define NUM_PPAACT_ENTRIES	512
+#define NUM_SPAACT_ENTRIES	256
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_TABLE_ALIGNMENT 0x00001000
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE  4096U
+
+#define PAACE_M_COHERENCE_REQ   0x01
+
+#define PAACE_DA_HOST_CR                0x80
+#define PAACE_DA_HOST_CR_SHIFT          7
+
+#define PAACE_AF_PT                     0x00000002
+#define PAACE_AF_PT_SHIFT               1
+
+#define PAACE_PT_PRIMARY       0x0
+#define PAACE_PT_SECONDARY     0x1
+
+#define PPAACE_AF_WBAL			0xfffff000
+#define PPAACE_AF_WBAL_SHIFT		12
+
+#define	OME_NUMBER_ENTRIES      16   /* based on P4080 2.0 silicon plan */
+
+#define PAACE_IA_CID			0x00FF0000
+#define PAACE_IA_CID_SHIFT		16
+#define PAACE_IA_WCE			0x000000F0
+#define PAACE_IA_WCE_SHIFT		4
+#define PAACE_IA_ATM			0x0000000C
+#define PAACE_IA_ATM_SHIFT		2
+#define PAACE_IA_OTM			0x00000003
+#define PAACE_IA_OTM_SHIFT		0
+
+#define PAACE_OTM_NO_XLATE      0x00
+#define PAACE_OTM_IMMEDIATE     0x01
+#define PAACE_OTM_INDEXED       0x02
+#define PAACE_OTM_RESERVED      0x03
+#define PAACE_ATM_NO_XLATE      0x00
+#define PAACE_ATM_WINDOW_XLATE  0x01
+#define PAACE_ATM_PAGE_XLATE    0x02
+#define PAACE_ATM_WIN_PG_XLATE  \
+	(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
+#define PAACE_WIN_TWBAL			0xfffff000
+#define PAACE_WIN_TWBAL_SHIFT		12
+#define PAACE_WIN_SWSE			0x00000fc0
+#define PAACE_WIN_SWSE_SHIFT		6
+
+#define PAACE_AF_AP			0x00000018
+#define PAACE_AF_AP_SHIFT		3
+#define PAACE_AF_DD			0x00000004
+#define PAACE_AF_DD_SHIFT		2
+#define PAACE_AF_PT			0x00000002
+#define PAACE_AF_PT_SHIFT		1
+#define PAACE_AF_V			0x00000001
+#define PAACE_AF_V_SHIFT		0
+#define PPAACE_AF_WSE			0x00000fc0
+#define PPAACE_AF_WSE_SHIFT		6
+#define PPAACE_AF_MW			0x00000020
+#define PPAACE_AF_MW_SHIFT		5
+
+#define PAACE_AP_PERMS_DENIED  0x0
+#define PAACE_AP_PERMS_QUERY   0x1
+#define PAACE_AP_PERMS_UPDATE  0x2
+#define PAACE_AP_PERMS_ALL     0x3
+
+#define SPAACE_AF_LIODN			0xffff0000
+#define SPAACE_AF_LIODN_SHIFT		16
+#define PAACE_V_VALID          0x1
+
+#define set_bf(v, m, x)             (v = ((v) & ~(m)) | (((x) << \
+					(m##_SHIFT)) & (m)))
+#define get_bf(v, m)            (((v) & (m)) >> (m##_SHIFT))
+
+#define DEFAULT_NUM_SUBWINDOWS		128
+#define PAMU_PCR_OFFSET 0xc10
+#define PAMU_PCR_PE	0x40000000
+
+struct pamu_addr_tbl {
+	phys_addr_t start_addr[10];
+	phys_addr_t end_addr[10];
+	phys_size_t size[10];
+};
+
+struct paace {
+	/* PAACE Offset 0x00 */
+	uint32_t wbah;			/* only valid for Primary PAACE */
+	uint32_t addr_bitfields;	/* See P/S PAACE_AF_* */
+
+	/* PAACE Offset 0x08 */
+	/* Interpretation of first 32 bits dependent on DD above */
+	union {
+		struct {
+			/* Destination ID, see PAACE_DID_* defines */
+			uint8_t did;
+			/* Partition ID */
+			uint8_t pid;
+			/* Snoop ID */
+			uint8_t snpid;
+			/* coherency_required : 1 reserved : 7 */
+			uint8_t coherency_required; /* See PAACE_DA_* */
+		} to_host;
+		struct {
+			/* Destination ID, see PAACE_DID_* defines */
+			uint8_t  did;
+			uint8_t  reserved1;
+			uint16_t reserved2;
+		} to_io;
+	} domain_attr;
+
+	/* Implementation attributes + window count + address & operation
+	 * translation modes
+	 */
+	uint32_t impl_attr;			/* See PAACE_IA_* */
+
+	/* PAACE Offset 0x10 */
+	/* Translated window base address */
+	uint32_t twbah;
+	uint32_t win_bitfields;			/* See PAACE_WIN_* */
+
+	/* PAACE Offset 0x18 */
+	/* first secondary paace entry */
+	uint32_t fspi;			/* only valid for Primary PAACE */
+	union {
+		struct {
+			uint8_t ioea;
+			uint8_t moea;
+			uint8_t ioeb;
+			uint8_t moeb;
+		} immed_ot;
+		struct {
+			uint16_t reserved;
+			uint16_t omi;
+		} index_ot;
+	} op_encode;
+
+	/* PAACE Offset 0x20 */
+	uint32_t reserved1[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x28 */
+	uint32_t reserved2[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x30 */
+	uint32_t reserved3[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x38 */
+	uint32_t reserved4[2];			/* not currently implemented */
+
+};
+
+int pamu_init(void);
+void pamu_enable(void);
+void pamu_disable(void);
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
+
+#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index fd8aba42a5..53ca6d94d6 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1935,7 +1935,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 	u8	res24[64];
 	u32	pblsr;		/* Preboot loader status */
 	u32	pamubypenr;	/* PAMU bypass enable */
-#define FSL_CORENET_PAMU_BYPASS		0xffff0000
 	u32	dmacr1;		/* DMA control */
 	u8	res25[4];
 	u32	gensr1;		/* General status */
@@ -2774,6 +2773,21 @@ typedef struct ccsr_pme {
 	u8	res4[0x400];
 } ccsr_pme_t;
 
+struct ccsr_pamu {
+	u32 ppbah;
+	u32 ppbal;
+	u32 pplah;
+	u32 pplal;
+	u32 spbah;
+	u32 spbal;
+	u32 splah;
+	u32 splal;
+	u32 obah;
+	u32 obal;
+	u32 olah;
+	u32 olal;
+};
+
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
 	u8	res0[0x543];
@@ -2854,6 +2868,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET	0xED000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
+#define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
@@ -3067,6 +3082,8 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 #define CONFIG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)