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| author | Marek Vasut <marex@denx.de> | 2015-07-09 05:21:02 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:07 +0200 |
| commit | bd65fe35fffd9a9e8c8abe5321a51a8c43eda97d (patch) | |
| tree | c791a32a4bdf363a7be4e9e4a2debcd3bbe92602 /arch | |
| parent | 232fcc6e9d5d13abba57994e6ee22e38e1321669 (diff) | |
| download | talos-obmc-uboot-bd65fe35fffd9a9e8c8abe5321a51a8c43eda97d.tar.gz talos-obmc-uboot-bd65fe35fffd9a9e8c8abe5321a51a8c43eda97d.zip | |
arm: socfpga: spl: Add missing reset logic
Make sure that all the peripherals are correctly reset and then
brought out of reset in the SPL. Not going through proper reset
cycle might leave the IP blocks in inconsistent state.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/spl.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 15fee0ad97..f134bb794f 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -89,6 +89,11 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + /* Put everything into reset but L4WD0. */ + socfpga_per_reset_all(); + /* Put FPGA bridges into reset too. */ + socfpga_bridges_reset(1); + socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); @@ -115,8 +120,9 @@ void spl_board_init(void) #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ - /* de-assert reset for peripherals and bridges based on handoff */ + /* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ @@ -145,4 +151,6 @@ void spl_board_init(void) puts("SDRAM size check failed!\n"); hang(); } + + socfpga_bridges_reset(1); } |
