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| author | Mingkai Hu <Mingkai.Hu@freescale.com> | 2015-11-11 17:58:34 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-30 09:11:10 -0800 |
| commit | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e (patch) | |
| tree | deb74cf668e12399f6fbf08a4e48434c6d3e3e85 /arch | |
| parent | 06b53010436bd7d4d0da6bdb2f505131a094abc6 (diff) | |
| download | talos-obmc-uboot-af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e.tar.gz talos-obmc-uboot-af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e.zip | |
pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
4 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 82991d5a79..5ce916c4d0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -50,6 +50,7 @@ #define CONFIG_SYS_FSL_CCSR_SCFG_LE #define CONFIG_SYS_FSL_ESDHC_LE #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -119,6 +120,7 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d941437d63..f52815d1fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -60,6 +60,10 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x10000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 134061c317..cd96604171 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -78,6 +78,10 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e4e2..86919065f3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; |
