diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2010-07-08 22:23:54 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-20 04:37:11 -0500 |
| commit | 99d9c07edc6e0b7b35694992f1cc40b540eec3ce (patch) | |
| tree | 3181566ea75183a90b45e2a318a391b33b51dfc7 /arch | |
| parent | 1f82ff4777f360e92aa37bbbed647f7b9d9d2044 (diff) | |
| download | talos-obmc-uboot-99d9c07edc6e0b7b35694992f1cc40b540eec3ce.tar.gz talos-obmc-uboot-99d9c07edc6e0b7b35694992f1cc40b540eec3ce.zip | |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4e665d3994..b1d219b7aa 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2060,8 +2060,17 @@ typedef struct ccsr_sec { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 +#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 +#else +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 +#endif #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 @@ -2138,6 +2147,17 @@ typedef struct ccsr_sec { #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_PCI1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) +#define CONFIG_SYS_PCI2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) +#define CONFIG_SYS_PCIE1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) +#define CONFIG_SYS_PCIE2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) +#define CONFIG_SYS_PCIE3_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) + #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) |
