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| author | Tom Rini <trini@konsulko.com> | 2015-09-13 17:25:16 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-09-13 17:25:16 -0400 |
| commit | 850f788709cef8f7d53d571aec3bfb73b14c5531 (patch) | |
| tree | 0641e0c973667223693da2b12c866460fd61af1c /arch | |
| parent | 4c669e2d3b0d65aeb5593c04b719284a41013c87 (diff) | |
| parent | 21871138b7686b36dd8ae97cab5dc1e9c5c6e183 (diff) | |
| download | talos-obmc-uboot-850f788709cef8f7d53d571aec3bfb73b14c5531.tar.gz talos-obmc-uboot-850f788709cef8f7d53d571aec3bfb73b14c5531.zip | |
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/rmobile/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rmobile/rcar-base.h | 3 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index ef56286715..85c06eb45f 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -40,6 +40,11 @@ config TARGET_PORTER select DM select DM_SERIAL +config TARGET_STOUT + bool "Stout board" + select DM + select DM_SERIAL + endchoice config SYS_SOC @@ -47,7 +52,7 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT default n choice @@ -80,5 +85,6 @@ source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" source "board/renesas/silk/Kconfig" source "board/renesas/porter/Kconfig" +source "board/renesas/stout/Kconfig" endif diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index d594cd77c1..53ead265bd 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -28,6 +28,9 @@ #define SCIF3_BASE 0xE6EA8000 #define SCIF4_BASE 0xE6EE0000 #define SCIF5_BASE 0xE6EE8000 +#define SCIFA0_BASE 0xE6C40000 +#define SCIFA1_BASE 0xE6C50000 +#define SCIFA2_BASE 0xE6C60000 /* Module stop status register */ #define MSTPSR0 0xE6150030 |
