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| author | Mans Rullgard <mans@mansr.com> | 2010-04-14 15:49:57 +0100 |
|---|---|---|
| committer | Sandeep Paulraj <s-paulraj@ti.com> | 2010-09-08 14:51:09 -0400 |
| commit | 096ca838b514be0a20e62500413e42f0a2bb7481 (patch) | |
| tree | bb66533e7f13d20a95770f911b947b736f9dd787 /arch | |
| parent | 29844707469854d9fab181edd6abe2f25fb5d208 (diff) | |
| download | talos-obmc-uboot-096ca838b514be0a20e62500413e42f0a2bb7481.tar.gz talos-obmc-uboot-096ca838b514be0a20e62500413e42f0a2bb7481.zip | |
ARMV7: OMAP3: Convert setup_auxcr() to pure asm
This function consists entirely of inline asm statements, so writing
it directly in a .S file is simpler. Additionally, the inline asm is
not safe as is, since registers are not guaranteed to be preserved
between asm() statements.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/board.c | 35 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/cache.S | 19 |
2 files changed, 19 insertions, 35 deletions
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 69e56f55c5..6c2a132b63 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -120,41 +120,6 @@ void secureworld_exit() } /****************************************************************************** - * Routine: setup_auxcr() - * Description: Write to AuxCR desired value using SMI. - * general use. - *****************************************************************************/ -void setup_auxcr() -{ - unsigned long i; - volatile unsigned int j; - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - /* Enabling ASA */ - __asm__ __volatile__("orr r0, r0, #0x10"); - /* Enable L1NEON */ - __asm__ __volatile__("orr r0, r0, #1 << 5"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */ - __asm__ __volatile__("mov r12, #0x2"); - __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2"); - __asm__ __volatile__("orr r0, r0, #1 << 27"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); -} - -/****************************************************************************** * Routine: try_unlock_sram() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index cb7ca11dab..5a19051191 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -43,6 +43,7 @@ .global invalidate_dcache .global l2_cache_enable .global l2_cache_disable +.global setup_auxcr /* * invalidate_dcache() @@ -156,3 +157,21 @@ l2_cache_disable: mov r0, #0 b l2_cache_set +/****************************************************************************** + * Routine: setup_auxcr() + * Description: Write to AuxCR desired value using SMI. + * general use. + *****************************************************************************/ +setup_auxcr: + mov r12, #0x3 + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x10 @ Enable ASA + orr r0, r0, #1 << 5 @ Enable L1NEON + .word 0xE1600070 @ SMC + mov r12, #0x2 + mrc p15, 1, r0, c9, c0, 2 + @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) + orr r0, r0, #1 << 27 + .word 0xE1600070 @ SMC + bx lr + |
